Terence G. W. Blake

Process for making high performance silicon-on-insulator transistor with body node to source node connection

High performance silicon-on-insulator transistor with body node to source node connection

Making a silicon-on-insulator transistor with selectable body node to source node connection

Single event upset hardened memory cell

Silicon-on-insulator transistor with body node to source node connection

MEMORY CELL WITH CAPACITANCE FOR SINGLE EVENT UPSET PROTECTION

MOS transistor with improved radiation hardness

Memory with p-channel cell access transistors

Output buffer having quasi-failsafe operation

Output buffer providing testability