Teresa L. McLaurin

ETM10 incorporates hardware segment of IEEE P1500

Engineers at ARM have used the ETM10 to incorporate the hardware segment of the IEEE P1500 standard. The experiments first phase incorporated the wrapper boundary register, wrapper bypass register, wrapper instruction register, and some standard instructions.

The testability features of the 3rd generation ColdFire/sup (R)/ family of microprocessors

A description of the DFT and test challenges faced, and the solutions applied, to the newest member of the ColdFire/sup (R)/ microprocessor family, the MCF5307, is described. The MCF5307 is the first member of the family to have on-chip, PLL-sourced, dual clock domains where the bus interface and the internal core microprocessor operate at different, but selectable, frequency ratios; and the internal microprocessor core of the MCF5307 was designed as a separate stand-alone core that contained multiple embedded memory arrays. The DFT challenges and solutions described involve the development of the at-speed AC scan test architecture and scan vectors in a multiple clock domain environment; the application of memory BIST to multiple embedded memories in a cost effective manner; and the handling of an on-chip PLL clock source.

Enhanced testing of clock faults

A test methodology for the control signals including clock logic, ripple reset and register file read/write control of the Cortex-A8trade high performance microprocessor core is presented. The target fault models include the stuck-at fault, transition fault and hold time fault models.

The testability features of the ARM1026EJ microprocessor core

The DFT and Test challenges faced, and the solutions applied, to the ARMl026EJ microprocessor core are described in this paper. New DFT techniques have been created to address the challenges of distributing a DFT core solution that will ultimately end up in many different environments. This core was instantiated into a test chip. The new DFT features were utilized successfully in the SOC.

The Challenge of Testing the ARM CORTEX-A8/sup TM/ Microprocessor Core

The DFT and test challenges faced, and the solutions applied, to the Cortex-A8 microprocessor core are described in this paper. New DFT techniques have been created to address the challenges of distributing a DFT core solution that ultimately end up in many different environments. This core comprises synthesized, hand-mapped, hand-placed (HMHP) and custom blocks. A DFT solution had to be created that could be utilized by a multitude of customers

Creating Structural Patterns for At-Speed Testing: A Case Study

Speed binning (or testing for functional frequency) often requires at-speed testing with functional patterns. Using structural patterns instead is an interesting alternative with respect to cost and overall coverage of nodes. This study analyzes the efficiency of structural test patterns when testing for frequency. Experiments with both path delay and transition delay patterns are discussed for multiple devices. The author shows how the tests are designed and what elements are taken into account to determine the best type of structural patterns.

The DFT challenges and solutions for the ARM® Cortex™-A15 Microprocessor

The DFT and test challenges faced, and the solutions applied, to the Cortex-A15 microprocessor core are described in this paper. New DFT techniques have been created to address the challenges of distributing a DFT flow that addresses multiple identical CPUs that will ultimately end up in many different design and test environments. We describe work done with EDA vendors to ensure that all mutual customers are able to implement this flow. In addition, this paper discusses the use of the ARM MBIST standardized interface in conjunction with a 3rd party MBIST controller for the first time. We collaborated closely with the 3rd party tool company and met all of the challenges to get this first time flow and tool capability working successfully on silicon.

A methodology for testing one-hot transmission gate multiplexers

There is a myriad of issues that arise when testing a device. One such issue is the testing of one-hot transmission gate (T-gate) multiplexers. Around the industry several different methodologies are used and additional hardware may be required to test this circuit. These methods may not address quality of test and not all of them is discussed in this paper. This paper show that a high quality test can occur on one-hot T-gate multiplexers without additional hardware

Test development for a third-version ColdFire microprocessor

The design-for-test methodology of the MCF5307 device is described, illustrating issues faced, how solutions were derived, and results.

The ARM Cortex-A8 Microprocessor IEEE Std 1500 Wrapper

This article describes the test wrapper implementation of a popular embedded microprocessor, along with an automated approach for verifying the wrappers compliance to the standard.