Michael Mateja

Scan based speed-path debug for a microprocessor

Identifying the actual speed limiting paths in silicon using traditional functional microprocessor tests can be very time-consuming and expensive because of limited observability of internal signals. This paper presents the development of a promising scan-based speed path diagnosis methodology and illustrates its application to a high performance microprocessor design.

Data learning techniques and methodology for Fmax prediction

The question of whether or not structural test measurements can be used to predict functional or system Fmax, has been studied for many years. This paper presents a data learning approach to study the question. Given Fmax values and structural delay measurements on a set of sample chips, we propose a method called conformity check whose goal is to select a subset of conformal samples such that a more reliable predictor can be built on. Our predictor consists of two models, a conformal model that decides on a given chip if its Fmax is predictable or not, and a prediction model that outputs the predicted Fmax based on results obtained from structural test measurements. We explain the data learning methodology and study various data learning techniques using frequency data collected on a high-performance microprocessor design.

The Test Features of the Quad-Core AMD Opteron- Microprocessor

This paper describes the design-for-test (DFT) features of the quad-core AMD-OpteronTM microprocessor.

Selecting the most relevant structural Fmax for system Fmax correlation

The use of low-cost structural Fmax measurement as a replacement for in-system Fmax measurement for speed binning has been aided by the use of a data-learning approach that can be used to build a reliable system Fmax predictor given structural Fmax. This paper uses industry test measurements to demonstrate why a data-learning approach for correlation is better than simple correlation approaches, how to select the most relevant structural Fmax, and how the proposed methodology works on multiple lots.

Mining AC delay measurements for understanding speed-limiting paths

Speed-limiting paths are critical paths that limit the performance of one or more silicon chips. This paper present a data mining methodology for analyzing speed-limiting paths extracted from AC delay test measurements. Based on data collected on 15 packaged silicon units of a four-core microprocessor design, we show that the proposed methodology can efficiently discovered actionable, design-related knowledge that would be difficult to find otherwise.

On evaluating speed path detection of structural tests

The detection of speed-related defects relies on fault excitation and propagation along critical speed paths in the design. Different types of structural tests detect speed paths differently. In this paper, we compare the capabilities of speed path detection using Ndetect and timing-aware transition tests on silicon. Experimental data on the latest quad-core AMD Opteron™ processor is collected. Results show either pattern set catches a significant amount of speed paths that is not predicted as critical timing paths. This illustrates the difficulty in pre-determine a subset of critical timing faults targeted for timing-aware transition test, while shows Ndetect transition test can be a practical solution for general speed path profiling.

Correlating system test Fmax with structural test Fmax and process monitoring measurements

System test has been the standard measurement to evaluate performance variability of high-performance microprocessors. The question of whether or not many of the lower-cost alternative tests can be used to reduce system test has been studied for many years. This paper utilizes a data-learning approach for correlating three test datasets, structural test, ring oscillator test, and scan flush test, with system test. With the data-learning approach, higher correlation can be found without altering test measurements or test conditions. Rather, the approach utilizes new optimization algorithms to extract more useful information in the three test datasets, with particular success using the structural test data. To further minimize test cost, process monitoring measurements (ring oscillator and scan flush tests) are used to reduce the need for high-frequency structural test. We demonstrate our methodology on a recent high-performance microprocessor design.

Test development for second-generation ColdFire microprocessors

This case study shows how test designers met fundamental microprocessor testing goals while adapting existing methodologies to a new architecture.

Test development for a third-version ColdFire microprocessor

The design-for-test methodology of the MCF5307 device is described, illustrating issues faced, how solutions were derived, and results.

A Path-Oriented Timing-Aware Diagnosis Methodology of At-Speed Transition Tests

Speed path identification is an indispensable step for pushing the design timing wall. We propose a new at-speed diagnosis methodology. Key characteristics of the methodology are (a) path-oriented diagnosis, (b) failing frequency guided, and (d) identified speed paths referenced in the timing verification design database. We demonstrate the effectiveness of our technique on a quad-core AMD Opteron (tm) Processor.