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Featured researches published by Terrence Caskey.


2007 32nd IEEE/CPMT International Electronic Manufacturing Technology Symposium | 2007

3D Electrical Interconnection Using Extrusion Dispensed Conductive Adhesives

Lawrence Douglas Andrews; Terrence Caskey; Simon J.S. Mcelrea

Electrical interconnections may be formed along the edges of stacked integrated circuits by an extrusion process that utilizes automated needle dispense equipment to form local deposits of conductive/adhesive polymer paste. This vertical interconnect process has been designed to form three- dimensional circuits without the imposition of significant mechanical forces that are known to cause mechanical damage to thin die or fragile substrate materials. The process has been demonstrated for both shingle-tier and vertical-stack configurations with productivity rates that exceed 100 interconnections per minute. Die-stacks of up to 128 chips have been demonstrated however, no current functional application can employ this design. In comparison with existing manufacturing methods for standard stacked-die packages, substantial packaging cost reductions are realized with this gang-based process due to the elimination of repeated die attach and pad-based wirebond processing steps, and the reduction or elimination of gold within the device.


Archive | 2008

Electrically interconnected stacked die assemblies

Simon J.S. Mcelrea; Lawrence Douglas Andrews; Scott McGrath; Terrence Caskey; Scott Jay Crane; Marc Robinson; Loreto Cantillep


Archive | 2008

Three-dimensional circuitry formed on integrated circuit device using two-dimensional fabrication

Lawrence Douglas Andrews; Simon J.S. Mcelrea; Terrence Caskey; Scott McGrath; Yong Du


Archive | 2014

Structure for microelectronic packaging with bond elements to encapsulation surface

Belgacem Haba; Ilyas Mohammed; Terrence Caskey; Reynaldo Co; Ellis Chau


Archive | 2008

Wafer level surface passivation of stackable integrated circuit chips

Simon J.S. Mcelrea; Terrence Caskey; Scott McGrath; DeAnn Eileen Melcher; Reynaldo Co; Lawrence Douglas Andrews; Weiping Pan; Grant Villavicencio; Yong Du; Scott Jay Crane; Zongrong Liu


Archive | 2008

Chip scale stacked die package

Simon J.S. Mcelrea; Marc Robinson; Lawrence Douglas Andrews; Terrence Caskey; Scott McGrath; Yong Du; Al Vindasius


Archive | 2013

Structure for microelectronic packaging with encapsulated bond elements

Belgacem Haba; Ilyas Mohammed; Terrence Caskey; Reynaldo Co; Ellis Chau


Archive | 2008

Electrical interconnect formed by pulsed dispense

Terrence Caskey; Lawrence Douglas Andrews; Simon J.S. Mcelrea; Scott McGrath; Jeffrey S. Leal


Archive | 2014

Low-stress TSV design using conductive particles

Charles G. Woychik; Kishor V. Desai; Ilyas Mohammed; Terrence Caskey


Archive | 2015

Reduced stress TSV and interposer structures

Cyprian Emeka Uzoh; Charles G. Woychik; Terrence Caskey; Kishor V. Desai; Huailiang Wei; Craig Mitchell; Belgacem Haba

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