Tetsufumi Kawamura

1.5-V Operating fully-depleted amorphous oxide thin film transistors achieved by 63-mV/dec subthreshold slope

Thin film transistors (TFTs) with a small subthreshold slope (SS) are urgently required for low-voltage operating circuits on large-area and flexible substrates. Using InGaZnO deposited at room temperature (RT), we achieved 63 mV/dec, the smallest-ever SS reported for oxide semiconductor TFTs. To achieve the small SS as well as small Ioff, a fully-depleted off-state was employed by thinning the channel layer to 6 nm. Scalability down to L = 2 mum was confirmed. For Vg = 0 to 1.5 V operation, Ioff <10-17 A/mum and on/off ratio > 108 were obtained.

Wireless operations for 13.56-MHz band RFID tag using amorphous oxide TFTs

This paper presents an RFID chip for 13.56-MHz band communication fabricated on a glass substrate by using amorphous In-Ga-Zn-O thin-film transistors. Low driving-voltage logic circuits were achieved with a small Vth, a high field effect mobility of 15cm2/Vs and “active load” inverters that had small consumption currents. The RFID tag was successively driven by 13.56-MHz wireless input.

Oxide TFT Rectifier Achieving 13.56-MHz Wireless Operation

We have fabricated a full-wave rectifier using fully depleted amorphous In-Ga-Zn-O thin-film transistors (TFTs). The rectifier is composed of four TFTs, and it rectified 13.56-MHz wireless input from a 200-mW commercial RFID reader/writer. We also have analyzed an output voltage and an operation frequency of the fabricated rectifier.

A Model for Predicting On-Current Degradation Caused by Drain-Avalanche Hot Carriers in Low-Temperature Polysilicon Thin-Film Transistors

A model for predicting on-current degradation caused by drain-avalanche hot carriers in NMOS low-temperature polysilicon thin-film transistors (TFTs) is described. The amount of trapped charge caused by hot-carrier stress was estimated by using a model describing the lightly doped drain region as an imaginary TFT, and it was found that the amount of trapped charge saturates as voltage-stress time passes. Moreover, the on-resistance increase caused by the trapped charge could be expressed as a function of voltage-stress time (t) , stress drain current (Id_str), and stress drain voltage (Vd_str), i.e., DeltaRon = Id_str exp(-beta/ Vd_str) AtB. This function can be used to predict the on-current degradation of TFTs after a long time for various gate lengths, operation voltages, and crystallinities of polysilicon.

Analysis of subthreshold slope of fully depleted amorphous In-Ga-Zn-O thin-film transistors

The behavior of the subthreshold slope (SS) of fully depleted (FD) amorphous In-Ga-Zn-O (a-InGaZnO) thin-film transistors (TFTs), which are n-type accumulation mode metal-oxide-semiconductor transistors, was analyzed. Thermal desorption spectra revealed that annealing was necessary to desorb H2 and H2O from the a-InGaZnO films for the FD mode operation along with small SS. Our experimental results indicated that the SS (a) increases with the increase in the thickness of the a-InGaZnO channel layer, (b) increases with the decrease in the oxygen partial pressure during the sputtering of the a-InGaZnO, (c) increases linearly with the increase in the thickness of the gate insulator, and (d) increases linearly with the increase in the temperature of the TFT. A theoretical equation that explains these results was derived by using the relations between the variations in the voltages applied to the electrodes and variations in the surface potentials derived from the charge conservation law. It was assumed during the derivation of the equation that the potential in the channel layer is the lowest along the back surface in the subthreshold region and most of the current flows there.

Self-boosted charge injection for 90-nm-node 4-Gb multilevel AG-AND flash memories programmable at 16 MB/s

This paper presents a high-speed multilevel programming scheme for 90-nm node AG-AND flash memories. Source-side hot-electron injection programming with self-boosted charge, accumulated in inversion-layer local bit-lines under AGs, reduces the dispersal of programming characteristics and also reduces the time overhead of pre-charging the bit-lines. With this self-boosted charge injection scheme, programming at a fast 16 MB/s is obtainable in 4-Gb flash memory with an actual cell size of 2F/sup 2//bit.

P‐17: Amorphous ZTO/ITO Stacked‐Channel TFTs with Field Effect Mobility over 50 cm2/Vs and Resistant to Channel Thickness Dispersion

We have developed bottom-gate amorphous-oxide TFTs with ZTO/ITO channel layers. The fabricated ZTO/ITO-TFTs demonstrated that threshold voltage (Vth) dispersion for TFTs with channel thickness dispersion was smaller one order of magnitude than that of conventional TFTs. Afield effect mobility of 52 cm2/Vs was obtained.

Negative-source enhanced source-side injection achieving 100-ns cell programming in multilevel flash memories

An enhanced source-side hot-electron injection scheme for a highspeed programming of multilevel flash memories has been developed. Applying a negative voltage at the source raises hot-electron injection efficiency and cell programming improves 20 times from the conventional scheme, achieving 100-ns cell programming. We have also developed a scheme generating negative source voltage by leveraging the capacitive coupling to achieve a narrow cell-programming-speed distribution along with the high speed.

A 126 mm/sup 2/ 4 Gb multilevel AG-AND flash memory with 10 MB/s programming throughput

A 4 Gb flash memory, fabricated in 90 nm CMOS technology, results in a 126 mm/sup 2/ chip size and a 0.0162 /spl mu/m/sup 2//b cell size. Address and temperature compensation methods control the resistance of the inversion-layer local bit-line. A programming throughput of 10 MB/s is achieved by using a self-boosted charge injection scheme.

Applying amorphous InGaZnO-TFT to RFID tag

Trial production of a thin-film radio frequency identification (RFID) tag with a built-in antenna was carried out using an amorphous InGaZnO (a-InGaZnO) thin-film transistor (TFT). A rectifier circuit, RF communication circuit, and logic circuit were formed using an a-InGaZnO TFT. Even after adding an antenna, which is the thickest part, the RFID itself had a thickness of about 1 μm. The RFID operated with a 13.56-MHz-band reader for IC cards and near field communication (NFC) devices. These results indicate the feasibility of an RFID tag that can be adhered to objects with a variety of shapes.