Jae-yoon Yoo

Fabrication of body-tied FinFETs (Omega MOSFETs) using bulk Si wafers

Nano scale body-tied FinFETs have been firstly fabricated. They have fin top width of 30 nm, fin bottom width of 61 nm, fin height of 99 nm, and gate length of 60 nm. This Omega MOSFET shows excellent transistor characteristics, such as very low subthreshold swing, Drain Induced Barrier Lowering (DIBL) of 24 mV/V, almost no body bias effect, and orders of magnitude lower I/sub SUB//I/sub D/ than planar type DRAM cell transistors.

Impact of mechanical stress engineering on flicker noise characteristics

Relationship between mechanical stress engineering and flicker noise are clarified for the first time using a 50nm level CMOS technology. It is found that enhanced mechanical stress degrades flicker noise characteristics. Trap states and dipoles generated by the stress are considered to be the cause of degradation. The transistor performance enhancement with flicker noise reduction by nitrogen profile optimization in gate dielectric is demonstrated as a countermeasure.

Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

In this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond. It offers increased Weff per active footprint and better performance compared to FinFET, and with a less complex patterning strategy, leveraging EUV lithography. Good electrostatics are reported at Lg=12nm and aggressive 44/48nm CPP (Contacted Poly Pitch) ground rules. We demonstrate work function metal (WFM) replacement and multiple threshold voltages, compatible with aggressive sheet to sheet spacing for wide stacked sheets. Stiction of sheets in long-channel devices is eliminated. Dielectric isolation is shown on standard bulk substrate for sub-sheet leakage control. Wrap-around contact (WAC) is evaluated for extrinsic resistance reduction.

Mature processability and manufacturability by characterizing V T and V min behaviors induced by NBTI and AHTOL test

A systematical reliability assessment for technology process that is essential for technology feasibility and qualification is presented by addressing physical and electrical characterization and reliability evaluation. By varying the duty cycle of enhanced pulsed radio frequency (eprf) technique used for the gate oxynitridation, the effects of nitrogen concentration and profile at SiO2/Si interface on VT and Vmin shift of thin oxide pMOSFET (∼20A) and SRAM, which result from negative bias temperature stability (NBTI) and accelerated high temperature operating life (AHTOL) stress test, are meticulously investigated. Using secondary ion mass spectrometry (SIMS) and high resolution Rutherford back scattering (H-RBS), nitrogen concentration and profile at the interface are carefully characterized. It is found that pMOSFET device processed with 10% of eprf provides ∼2× longer NBTI lifetimes than with 20% of eprf due to lower nitrogen concentration at the interface. Furthermore, Vmin shift of SRAM with 10% of eprf, which is caused by AHTOL test conditioned at 140°C with 1.4× Vdd, is ∼3∼4× less than with 20% of eprf. In fact, a nano-probing technique elucidates that Vmin shift is mainly attributed to the mismatch of VT between pull-up (PU) transistors in SRAM induced by NBTI stemmed from AHTOL test. It is also empirically shown that Vmin shift behavior is in good agreement with the read margin rather than the write. Accordingly, a stabilized Vmin drift behavior consistently adheres to the write margin. Hence, the optimization of interfacial nitrogen concentration results in less pMOSFET NBTI degradation so as to efficiently suppress Vmin shift of SRAM. Besides, increasing PU transistor size that decreases the γ value (the ratio of Ion current of PG to PU) can also reduce Vmin shift during AHTOL test. Finally, mature processability and manufacturability are attained by characterizing VT and Vmin behaviors for pMOSFET and SRAM from the front-end-of-line (FEOL) process optimization and SRAM bit-cell design aspect.

Issues of Ultrashallow Junction for Sub-50 nm Gate Length Transistors: Metrology, Dopant Loss, and Novel Electrostatic Junction

Issues of ultrashallow junctions (USJ) for sub-50 nm gate-length transistors are discussed. To measure the actual current drivability of source/drain extension (SDE), we developed SDE sheet resistance test structure (SSTS) which simulates the actual geometry and thermal condition of dopant underneath sidewall spacer. By using low energy electron induced X-ray emission spectrometry (LEXES) and other conventional techniques such as four point probe (FPP) and secondary ion mass spectrometry (SIMS), we quantified SDE dopant loss during the CMOS process and found that the wet-etching removal and outdiffusion are the most significant causes for dopant loss in n-SDE and p-SDE, respectively. Novel junction structures with electrostatic channel extension (ESCE) MOSFET for sub-20 nm gate-length transistor are presented as well