Tetsuo Tada

Test cost reduction by at-speed BISR for embedded DRAMs

The increase of test time of embedded DRAMs (e-DRAM) is one of the key issues of System-on-chip (SoC) device test. This paper proposes putting the repair analysis function on chip as Built In Self Repair (BISR). BISR is performed at 166 MHz as at-speed of e-DRAM using low cost automatic test equipment (ATE). The area of the BISR is approximately 1.7 mm/sup 2/, about 2% of conventional SoC devices. Using an error storage table form contributes to realizing a small area penalty of the repair analysis function. e-DRAM functional test time was reduced about 20% less than the conventional method at wafer level testing. Moreover, the results of e-DRAM test and repair analysis using BISR is almost coincident with the conventional method.

A fine pitch probe technology for VLSI wafer testing

The limitations of the cantilevered wire probe card with respect to both pin count and pin pitch are pointed out. The authors then present the structure and electric characteristics of a novel wafer probe card and its prototype with 80- mu m pitch and 479 electrodes, obtained by etching a photosensitive transparent glass. With this probe-card technology it is possible to probe LSI with higher pin count and finer pitch pads.<<ETX>>

Composite- Type pin Grid Array package

A composite pin grid array (PGA) package was developed. This package is composed of the base, the polyimide film with the wiring paths of copper, and the cap. An attractive feature of this package is its electrical performance. Moreover, this package is suitable both for customization and for mass production at relatively low cost with reduced lead time from design to production.