Hideshi Maeno

A novel memory cell for multiport RAM on 0.5 /spl mu/m CMOS Sea-of-Gates

A novel memory cell circuit for multiport RAM on CMOS Sea-of-Gates (SOG) has been proposed. It contributes to the operation both at high speed and at low voltage. In addition, a fourfold read bit line technique is also proposed to reduce the access time. A multiport RAM generator with the novel memory cell has been developed. 2-port or 3-port RAMs with flexible bit-word configurations are available. Test chips containing seven generated RAMs were designed and fabricated on 0.5 /spl mu/m CMOS SOG. The experimental results of the chip show that each RAM operates at over 1.4 V and that the address access time of the 3-port RAM (16b/spl times/256w) is 4.8 ns at 3.3 V. >

A multi-port RAM generator with novel memory cell for CMOS Sea-of-Gates

A multi-port RAM generator for 0.5 /spl mu/m CMOS Sea-of-Gates (SOG) has been developed. 2-port or 3-port RAMs with flexible bit-word configurations are available. In order to operate either at a low supply voltage or at high speed, a novel memory cell circuit is proposed. In addition, a fourfold real bit line technique is adopted to improve access time. The experimental results of the test chips show that each generated RAM operates at over 1.4 V and that the address access time of the 3-port RAM (16 b/spl times/256 w) is 4.8 ns at 3.3 V.<<ETX>>