Tetsuro Kawata

An outline font rendering processor with an embedded RISC CPU for high-speed hint processing

Font rendering requires state-of-the-art hint processing for delicate adjustment to output devices in practical applications. The hint processing is a function which corrects transformed outlines using additional information. A font rendering processor has been developed using a CMOS 0.8 /spl mu/m pg process on a 9.47/spl times/9.24 mm/sup 2/ die. It incorporates the hint processing capability, and thus unburdens a host CPU of the whole font rendering. It comprises a RISC CPU for high-speed hint processing and special hardware units that is based upon a DDA and an edge flag algorithm for outline drawing and filling. A performance evaluation using the fabricated chip has shown about 0.4 ms/char and 1.5 ms/char rendering capability for small size alphabets and Kanjis, respectively. It equals about 7-11 times performance compared to a Sparc Station 2, and from about 22-38 times performance compared to a Sun4/110. >

Parallel processor system specific for Monte Carlo analysis based on ring bus architecture

We have developed a new parallel processor system specific for the MC analysis, to dramatically reduce the calculation time. Our parallel processor system is based on ring bus architecture. The RISC micro processor chip, which contains a ring bus interface unit (RBIU), a floating point arithmetic unit (FAU) and so on, was also developed for our system. Speed up ratio compared with a single processor reached to 13.5 at 23 PEs.