Nobuaki Miyakawa

Future system-on-silicon LSI chips

A new three-dimensional (3D) integration technology to achieve system-on-silicon LSIs has been proposed. Several LSI wafers are vertically stacked and glued each other after thinning them in this 3...The development of system-on-silicon large-scale integration (LSI) devices has significantly influenced the demand for higher wiring connectivity within LSI chips. Currently, increasing the number of metal layers in a multilevel metallization as the device size decreases increases wiring connectivity. In the future, however, designers will have difficulty catching up with the rising demand for higher wiring connectivity by merely increasing the number of metal layers. We propose a new three-dimensional integration technology to overcome future wiring connectivity crises. In our solution, several vertically stacked chip layers in 3D LSI chips or 3D multichip modules (MCMs) are fabricated using our new integration technology. More than 10/sup 5/ interconnections per chip form in a vertical direction in these 3D LSI chips or 3D MCMs. Consequently, we can dramatically increase wiring connectivity while reducing the number of long interconnections.

Intelligent image sensor chip with three dimensional structure

A new three-dimensional (3D) integration technology based on wafer bonding technique has been proposed for intelligent image sensor chip with 3D stacked structure. We have developed key technologies for such 3D integration. A 3D image sensor test chip was fabricated using this 3D integration technology. Basic electric characteristics were evaluated in the 3D image sensor test chip.

New Three-Dimensional Wafer Bonding Technology Using the Adhesive Injection Method

A new three-dimensional (3D) wafer bonding technology using the adhesive injection method has been proposed, in order to realize a real-time micro-vision system and a real shared memory. Several key technologies for 3D LSI, such as deep trench formation for buried interconnection, wafer grinding and chemical-mechanical polishing, wafer alignment and wafer bonding using the adhesive injection method, have been developed.

DEVELOPMENT OF MD ENGINE : HIGH-SPEED ACCELERATOR WITH PARALLEL PROCESSOR DESIGN FOR MOLECULAR DYNAMICS SIMULATIONS

Application of molecular dynamics (MD) simulations to large systems, such as biological macromolecules, is severely limited by the availability of computer resources. As the size of the system increases, the number of nonbonded forces (Coulombic and van der Waals interactions) to be evaluated increases as 𝒪(N2), where N is the number of particles in the system. The force evaluation consumes more than 99% of the CPU time in an MD simulation involving over 10,000 particles. Hence, the major target for reduction of the CPU time should be acceleration of the calculation of nonbonded forces. For this purpose, we developed a custom processor for calculating nonbonded interactions and a scalable plug‐in machine (to a workstation), the MD Engine, in which numbers of the custom processors work in parallel. The processor has a pipeline architecture to calculate the total nonbonded force using the coordinates, electric charge, and species of each particle broadcast by the host computer. The force is calculated with sufficient accuracy for practical MD simulations. The processor also calculates virials simultaneously with forces for use in the calculation of pressure, accommodates periodic boundary conditions, and can be used in Ewald summations. An MD Engine system consisting of 76 processors calculates nonbonded interactions about 50 times faster than an UltraSPARC‐I processor (Sun Ultra‐2, 200 MHz) or an R10000 processor (SGI Origin 200, 180 MHz). On a Sun Ultra‐2 workstation with a single UltraSPARC‐I processor an MD simulation of a Ras p21 protein molecule immersed in a water sphere (13,258 particles) was accelerated by a factor of 48 using the MD Engine system. ©1999 John Wiley & Sons, Inc. J Comput Chem 20: 185–199, 1999

Development of Three-Dimensional Integration Technology for Highly Parallel Image-Processing Chip

A new three-dimensional (3D) integration technology for realizing a highly parallel image-processing chip has been developed. Several LSI wafers are vertically stacked and glued to each other after thinning them using this new technology. This technology can be considered as both 3D LSI technology and wafer-scale 3D chip-on-chip packaging technology. The effective packaging density can be significantly increased by stacking the chips in a vertical direction. Several key techniques for this 3D integration have been developed. In this paper, we demonstrate the highly parallel image sensor chip with a 3D structure. The 3D image sensor test chip was fabricated using this new 3D integration technology and its basic performance was evaluated.

Three-dimensional integration technology for real time micro-vision system

It becomes possible to achieve the real time micro-vision system with extremely high image processing speed if three-dimensional LSI comes into reality because a higher level of parallel processing can be performed in three-dimensional LSI. Then, we have proposed a new three-dimensional integration technology for such real time micro-vision system with high image processing speed. Several key technologies for three-dimensional integration such as formation of buried interconnection and micro-bump, wafer thinning, wafer alignment and wafer bonding have been developed.

A novel parallel algorithm for large‐scale Fock matrix construction with small locally distributed memory architectures: RT parallel algorithm

We developed a novel parallel algorithm for large‐scale Fock matrix calculation with small locally distributed memory architectures, and named it the “RT parallel algorithm.” The RT parallel algorithm actively involves the concept of integral screening, which is indispensable for reduction of computing times with large‐scale biological molecules. The primary characteristic of this algorithm is parallel efficiency, which is achieved by well‐balanced reduction of both communicating and computing volume. Only the density matrix data necessary for Fock matrix calculations are communicated, and the data once communicated are reutilized for calculations as many times as possible. The RT parallel algorithm is a scalable method because required memory volume does not depend on the number of basis functions. This algorithm automatically includes a partial summing technique that is indispensable for maintaining computing accuracy, and can also include some conventional methods to reduce calculation times. In our analysis, the RT parallel algorithm had better performance than other methods for massively parallel processors. The RT parallel algorithm is most suitable for massively parallel and distributed Fock matrix calculations for large‐scale biological molecules with more than thousands of basis functions.

An outline font rendering processor with an embedded RISC CPU for high-speed hint processing

Font rendering requires state-of-the-art hint processing for delicate adjustment to output devices in practical applications. The hint processing is a function which corrects transformed outlines using additional information. A font rendering processor has been developed using a CMOS 0.8 /spl mu/m pg process on a 9.47/spl times/9.24 mm/sup 2/ die. It incorporates the hint processing capability, and thus unburdens a host CPU of the whole font rendering. It comprises a RISC CPU for high-speed hint processing and special hardware units that is based upon a DDA and an edge flag algorithm for outline drawing and filling. A performance evaluation using the fabricated chip has shown about 0.4 ms/char and 1.5 ms/char rendering capability for small size alphabets and Kanjis, respectively. It equals about 7-11 times performance compared to a Sparc Station 2, and from about 22-38 times performance compared to a Sun4/110. >

GRAPE-3: highly parallelized special-purpose computer for gravitational many-body simulations

The authors have developed a highly parallelized special-purpose computer GRAPE (GRAvity PipE)-3 for gravitational many-body simulations. It accelerates gravitational force calculations which are the most expensive part of the many-body simulations. The peak computing speed is equivalent to about 15 GFLOPS. The GRAPE-3 system consists of two identical boards connected to a host computer through a VME bus. Each board has 24 custom LSI GRAPE chips which calculate gravitational forces in parallel. The gravitational force calculation is easily parallelized because the forces on different particles con be calculated independently. Using the pipelined architecture, one GRAPE chip calculates one gravitational force between a pair of particles at every clock cycle. The number of floating point operations needed to calculate one force is about 90. Therefore, one GRAPE chip running at 10 MHz clock-rate has a computing speed equivalent to 0.3 GFLOPS. The GRAPE-3 with 48 GRAPE chips achieves about 15 GFLOPS. One GRAPE chip has 110000 transistors in an 8 mm*8 mm area and its power consumption is 1.2 W at 10 MHz. Its package is ceramic PGA with 181 pins. One GRAPE-3 board is a 9U Eurocard, on which 159 chips are wire-wrapped.<<ETX>>

GRAPE: special purpose computer for simulations of many-body systems

The authors are developing a series of special-purpose computers, GRAPE (GRAvity PipE), for simulations of many-body systems such as star clusters and systems of molecules. In simulations of many-body systems, almost all the computing time is consumed in the calculation of the force between the particles. A host computer sends the positions of the particles to GRAPE, which then calculates the force exerted on a particle and sends it back to the host computer. The host updates the positions, velocities, etc., of the particles. The machines with odd numbers (GRAPE-1, GRAPE-1A, GRAPE-3, and GRAPE-3A) belong to the low-accuracy type. The machines with even numbers (GRAPE-2 and GRAPE-2A) belong to the high-accuracy type. GRAPE-2A was designed for the application of molecular dynamics simulations as well as gravitational many-body simulations. The computational speed of GRAPE-2A is about 180 MFLOPS. The authors are designed a highly parallel machine, GRAPE-4, in which many GRAPE pipelines work in parallel.<<ETX>>