Thais Webber

GTAexpress: A Software Package to Handle Kronecker Descriptors

This paper presents a software package, called GTAexpress, to handle structured continuous-time Markovian models expressed using Generalized Tensor Algebra, also known as, Kronecker descriptors. The proposed software package has the most advanced methods to provide stationary and transient solutions as well as some basic structural properties of models represented as a sum of generalized tensor products. Other software tools already provide some approaches based on tensor representation, like, PEPS and SMART. However, such tools are bounded to a specific modeling formalism. The basic idea of GTAexpress is to provide Kronecker descriptor-based solutions that can be easily used as a package in new tools or as a library in the existing high-level formalisms tools.

Exploiting Modbus Protocol in Wired and Wireless Multilevel Communication Architecture

This paper proposes an architectural improvement for the Modbus RTU protocol to integrate equipments in industrial automation networks, employing hybrid communication with wired Modbus RTU and wireless IEEE 802.15.4. These environments have different electromagnetic interferences, requiring protocols with noise immunity to varied equipments such as motors and generators. Modbus RTU is a simple and robust master-slave protocol that accepts the integration of a master with up to 247 slaves into a bus topology. In addition, the IEEE 802.15.4 protocol emerged recently as a wireless solution to industrial environments since it allows electromagnetic spectrum evaluation, and the choice of avoiding communications in noise frequencies and decreasing the error rate between packets. The proposed hybrid communication protocol increases control and topological limits imposed by Modbus RTU by enabling a wired/wireless tree-bus topology and master multiplexing. Moreover, the academy-industry cooperation resulted in features implemented in a gateway, whose efficiency is evaluated with practical experiments in different topologies.

Analytical Modeling of Software Development Teams in Globally Distributed Projects

Global software engineering is an area of increasing research challenges, in which teams are dispersed in multiple sites collaborating across borders and time zones. In spite of its potential competitive advantages, globally distributed projects must deal with difficulties when distributing resources such as teams with cultural diversities, different skills and experience levels. Both industry and academia demonstrate a special interest in the modeling and prediction, mainly representing systems in order to extract interesting indices, for example, evaluating whether or not a project will succeed. This paper demonstrates the usefulness of analytical modeling techniques in order to predict the outcome of geographically-distributed projects. We focus our attention to the participants interaction and its interplay when it affects team productivity. The models are parametrized considering single-site and multi-site scenarios, varying resources availability, teams expertise and support levels. Performance indices from both scenarios are presented and conclusion indicates possible model extensions.

Tiny NoC: A 3D Mesh Topology with Router Channel Optimization for Area and Latency Minimization

This paper presents Tiny NoC, which is a scalable and efficient 3D mesh architecture developed to minimize latency and NoC area. First, we show a theoretical analysis of latency and area occupancy to demonstrate Tiny NoC efficiency when compared to a basic mesh NoC. Then, we select a set of synthetic and mapping independent traffic with several injection rates to analyze the advantages and weaknesses of Tiny NoC. The experimental results highlight that Tiny NoC always reduces area occupancy and for several cases it provides latency minimization.

Lasio 3D NoC vertical links serialization: Evaluation of latency and buffer occupancy

Communication plays a crucial role in the design of high performance Multiprocessor Systems-on-Chip (MPSoC). Accordingly, Networks-on-Chip (NoC) have been successfully employed as a solution to deal with communication in complex MPSoCs. NoC-based architectures are characterized by various tradeoffs related to structural characteristics, performance specifications, and application demands. In new technologies, the relative values of wire delays and power consumption are increasing as the number of cores in 2D chips increase. The recent 3D IC technology applied to NoC architectures allows greater device integration and shorter interconnection links, which directly influences the communication performance. Through-Silicon Vias (TSVs) are used for the interconnection between vertical layers of a 3D IC. The drawback is that TSVs are usually very expensive in terms of silicon area, limiting their usage. This work explores the serialization of vertical links, employing a TSV multiplexing scheme for Lasio, a 3D mesh NoC. We implemented and analyzed the impact in network and application latency and in the occupancy of input buffers for a 4×4×4 mesh NoC with different multiplexing degrees, which imply different levels of TSV usage reduction and serialization. Results demonstrate that the proposed scheme allows reducing TSV usage with low performance overhead, pointing to potential benefits of the scheme in 3D NoC-based MPSoCs.

Efficient vector-descriptor product exploiting time-memory trade-offs

The description of large state spaces through stochastic structured modeling formalisms like stochastic Petri nets, stochastic automata networks and performance evaluation process algebra usually represent the infinitesimal generator of the underlying Markov chain as a Kronecker descriptor instead of a single large sparse matrix. The best known algorithms used to compute iterative solutions of such structured models are: the pure sparse solution approach, an algorithm that can be very time efficient, and almost always memory prohibitive; the Shuffle algorithm which performs the product of a descriptor by a probability vector with a very impressive memory efficiency; and a newer option that offers a trade-off between time and memory savings, the Split algorithm. This paper presents a comparison of these algorithms solving some examples of structured Kronecker represented models in order to numerically illustrate the gains achieved considering each models characteristics.

Parallel PEPS Tool Performance Analysis Using Stochastic Automata Networks

This paper presents a theoretical performance analysis of a parallel implementation of a tool called Performance Evaluation for Parallel Systems (PEPS). This software tool is used to analyze Stochastic Automata Networks (SAN) models. In its sequential version, the execution time becomes impracticable when analyzing large SAN models. A parallel version of PEPS using distributed memory is proposed and modelled with SAN formalism. After, the sequential PEPS itself is applied to predict the performance of this model.

Stochastic Model for QoS Assessment in Multi-tier Web Services

Service Level Agreements (SLAs) are used to guarantee quality of service (QoS) between customers and service providers. In an SLA, parties establish a common set of rules and responsibilities. In this paper we propose a practical stochastic modeling of a multi-tier architecture considering SLAs for specific transactions. The model is parameterized with available performance testing data for a real web service, and with a testing environment having unpredictable and unknown external workloads of simultaneous execution. In addition, we present multiple scenarios of external applications impacting on the SLAs in our target architecture. Having a previous knowledge about the average time demanded by some external applications, our model results can provide evidences when the system under test will not respect the agreed-upon SLAs. Finally, we discuss possible model extensions towards further unknown workload characterizations and considerations about application execution profiling.

Phoenix NoC: A distributed fault tolerant architecture

The advances in deep submicron technology have made the development of large Multiprocessor Systems-on-Chip (MPSoC) possible and Networks-on-Chip (NoCs) have been recognized to provide an efficient communication architecture for such systems. With the positive effects on the devices integration some drawbacks arise, such as the increase of fault susceptibility during the MPSoC manufacturing and operation. This work presents Phoenix, which is a direct mesh NoC that implements fault tolerant mechanisms in order to enable end-to-end communication when some links fail. Phoenix implements a distributed fault tolerant mechanism in software (i.e. in each processor) and in hardware (i.e. in each router). Experimental results show that Phoenix is scalable and allows the MPSoC operation even in the presence of several faulty links.

Kronecker descriptor partitioning for parallel algorithms

The key operation to obtain stationary and transient solutions of transition systems described by Kronecker structured formalisms is the Vector-Descriptor product. This operation is usually performed with shuffling operations and matrices aggregations to reduce the floating point multiplications inside iterative methods. Due to the flexibility of the Split method treating Kronecker product terms, it is a natural alternative to decompose descriptors within parallel environments. The main problem is to define the correct task size to assign to each node and also the shared memory size, since sending a small task per time can lead to a larger communication overhead. In this paper we are investigating data partitioning strategies for a parallel solution of transition systems obtained from Kronecker descriptors using the Split algorithm.