Thaísa Leal da Silva

FPGA Based Design of CAVLC and Exp-Golomb Coders for H.264/AVC Baseline Entropy Coding

This paper presents the design of a hardware architecture for the entropy coder of H.264/AVC video compression standard, considering the baseline profile. The baseline entropy coder is composed of two main blocks: Exp-Golomb coder and CAVLC coder. This paper presents the architectural design of these two blocks. These architectures were described in VHDL and synthesized to an Altera Stratix-II FPGA. From the synthesis results it was possible to verify that the Exp-Golomb and CAVLC coders reached a throughput of 15.9 million of samples per second for the Exp-Golomb coder and of 103.8 million of samples per second for CAVLC coder. The H.264/AVC baseline entropy coder is being designed through the integration of these two coders and preliminary results indicate that this solution will be able to process HDTV frames in real time.

Complexity reduction of depth intra coding for 3D video extension of HEVC

Three dimensional (3D) video technology, systems and applications such as 3D television and freeviewpoint television (FTV) broadcasts require efficient encoding of video information. To fill that need a 3D video extension of High Efficiency Video Coding standard, called 3D-HEVC, is being developed. This extension is based on Multiview Video plus Depth (MVD) format, which associates a depth information to each texture frame of each view. This paper presents a method to accelerate the intra coding of these depth maps to reduce the 3D-HEVC computational complexity. The proposed algorithm exploits the edge orientation of the depth blocks to reduce the number of modes to be evaluated in the intra mode decision. In addition, the correlation between the Planar mode choice and the most probable modes (MPMs) selected is also exploited, to accelerate the depth intra coding. The experimental results show that the proposed algorithm achieves an average complexity reduction of 15% on depth information encoding, with a small degradation in encoding efficiency (BD-rate increase of 0.16% on average).

HEVC intra mode decision acceleration based on tree depth levels relationship

The new High Efficiency Video Coding (HEVC) standard is achieving higher encoding efficiency when compared to its predecessors such as H.264/AVC. One of the factors responsible to this improvement is the intra prediction method, which introduces a larger number of prediction directions resulting in an enhanced rate-distortion (RD) performance at the cost of a higher computational complexity. This paper proposes an algorithm to accelerate the intra mode decision, reducing the complexity of intra coding. The acceleration procedure takes into account the edge direction information and explores the correlation of intra modes across levels of the HEVC hierarchical tree structure. Experimental results show that the proposed algorithm provides a decrease of up to 40.82% in the HEVC intra prediction processing time, with a small degradation in encoding efficiency (BD-PSNR loss of 0.1 dB on average).

Fast mode selection algorithm based on texture analysis for 3D-HEVC intra prediction

The increasing availability of 3D video systems and applications has attracted more consumers for 3D viewing experiences and, consequently, the demand for storage and transmission of 3D video content is growing. An interesting alternative for this need is the transmission of 3D video based on the Multiview Video plus Depth (MVD) format. The upcoming 3D High Efficiency Video Coding (3D-HEVC) standard will adopt this format, which associates a depth map to each texture frame. This paper presents a fast mode decision algorithm, which analyses the texture frames and depth maps to detect the edge orientation of the prediction units (PUs), optimizing the intra prediction process and reducing the 3D-HEVC computational complexity. The experimental results show that the proposed algorithm achieves an average processing time reduction of 26.2%, with a small degradation in encoding efficiency (BD-rate increase of 0.3% on average).

Inter-view prediction of coding tree depth for HEVC-based multiview video coding

Seeking for higher encoding efficiency, the emerging High Efficiency Video Coding (HEVC) standard has adopted new encoding techniques such as recursive quadtree structure, flexible block partitioning and larger size blocks. However, this improved efficiency leads to greater computational complexity. This paper deals with complexity reduction of the HEVC-based multiview video coding proposing a new inter-view prediction technique, fully compliant with the HEVC standard. This new technique uses the coding unit (CU) tree depths used in the base view as a depth threshold to be used in the dependent views. When compared to HEVC simulcast the proposed method achieves a complexity reduction of up to 50.32%, at the cost of an average BD-PSNR loss of 0.03 dB.

Inter-view prediction of intra mode decision for high-efficiency video coding-based multiview video coding

Abstract. Intra prediction is a very important tool in current video coding standards. High-efficiency video coding (HEVC) intra prediction presents relevant gains in encoding efficiency when compared to previous standards, but with a very important increase in the computational complexity since 33 directional angular modes must be evaluated. Motivated by this high complexity, this article presents a complexity reduction algorithm developed to reduce the HEVC intra mode decision complexity targeting multiview videos. The proposed algorithm presents an efficient fast intra prediction compliant with singleview and multiview video encoding. This fast solution defines a reduced subset of intra directions according to the video texture and it exploits the relationship between prediction units (PUs) of neighbor depth levels of the coding tree. This fast intra coding procedure is used to develop an inter-view prediction method, which exploits the relationship between the intra mode directions of adjacent views to further accelerate the intra prediction process in multiview video encoding applications. When compared to HEVC simulcast, our method achieves a complexity reduction of up to 47.77%, at the cost of an average BD-PSNR loss of 0.08 dB.

HEVC intra prediction acceleration based on texture direction and prediction unit modes reuse

The new High Efficiency Video Coding (HEVC) standard achieves higher encoding efficiency when compared to its predecessors such as H.264/AVC. One of the factors responsible for this improvement is the new intra prediction method, which introduces a larger number of prediction directions resulting in an enhanced rate-distortion (RD) performance obtained at the cost of higher computational complexity. This paper proposes an algorithm to accelerate the intra mode decision, reducing the complexity of intra coding. The acceleration procedure takes into account the texture local directionality information and explores the correlation of intra modes across levels of the hierarchical tree structure used in HEVC. Experimental results show that the proposed algorithm provides a decrease of 39.22 and 43.88 in the HEVC intra prediction processing time on average, for allintra high efficiency (AI-HE) and low complexity (AI-LC) configurations, respectively, with a small degradation in encoding efficiency (BD-PSNR loss of 0.1 dB for AI-HE and 0.8 dB for AI-LC on average).

A novel macroblock-level filtering upsampling architecture for H.264/AVC scalable extension

The scalable extension of the H.264/AVC standard (loosely called H.264/SVC) uses spatial upsampling in the spatial scalability modes. This work presents a novel upsampling architecture designed for operation at macroblock level and dyadic upsampling ratio with QVGA as the base layer resolution and VGA as the enhancement resolution. The adoption of a macroblock-level solution translates into a more efficient use of hardware resources with savings of approximately 25% in the number of ALUTs and DLRs and using about two hundred times less memory bits, when compared to previously published works. Moreover the timing analysis results show that this architecture has a worst-case processing rate of 465 VGA frames per second, far exceeding the throughput necessary to decode VGA resolution videos in real time.