Thanas Budri

Effects of Boron and Germanium Base Profiles on SiGe and SiGe:C BJT Characteristics

We present results of an experiment with different boron and germanium profiles aimed at the optimization of the vertical profile in SiGe BJT. Simulation and experimental results show the importance of correct positioning of the germanium profile relative to boron profile to achieve maximum fTpeak. Introduction of the low-doped base region at the emitter side if well optimized improves the base current ideality and low-current fT without fTpeak reduction.

Raman spectroscopy analysis utilized to identify stress induced leakage from power and high speed technologies using deep trench isolation schemes

Power and Advanced BiCMOS technologies use deep trench architecture to reduce capacitance and leakages that are enhanced by high electric fields and high current applications. In this paper, a power and an advanced BiCMOS technology with deep trench architectures used micro Raman spectroscopy to identify non-uniform stress regions in the circuit. Using this information, architectural changes were implemented to reduce the overall stress and subsequent leakage. In both cases, multiprobe yields were increased due to the reduced circuit leakage.

Full wafer defect analysis with time-of-flight secondary Ion Mass Spectrometry

ToF-SIMS was used for defect and failure analysis on full wafers using KLA/Tencor maps for addressing selected defects for analysis. In the first case study, analysis of surface contamination is discussed. The analysis was performed in microscan mode for single particle analysis or in macroscan mode for large area analysis. In a second example, ToF-SIMS was used to identify particle type metallic defects from a P-type buried layer of BiCMOS transistors under 200 nm of SiO2. The last case study discusses the detection of unintentionally implanted P in micron-sized polysilicon lines in the active punch-through area of a wafer.

Developing a high volume manufacturing method to eliminate P Buried Layer implant defects

Atomic Force Microscopy, Deep Level Transient Spectroscopy and Secondary Ion Mass Spectroscopy were used to study defects created in the P Buried Layer while using a BF2 implant. The P Buried Layer defects were traced to the unintentional co-implantation of Mo along with the BF2 implant. Using a Tungsten source, instead of a Molybdenum source for the BF2 implant, reduced but did not eliminate these defects. A novel, high volume processing method was developed to produce metal contamination-free buried layers and verified by deep level transient spectroscopy spectra.

In Line Wafer Mapping TXRF Analysis Supporting Process Improvements and Process Development

Wafer mapping TXRF is used as a process optimization tool in metal etch, silicon nitride deposition and chemical mechanical polish.

TXRF Applications Supporting Yield Enhancements and Tool Monitor-ing in Order to Improve the Front-End Semiconductor Processing

In this paper, we summarize how the introduction of in-line TXRF monitoring provides detailed analytical information on aluminum, titanium and molybdenum contamination levels in order to improve several process steps from front- end processing, minimize product yield loss and make it possible to successfully manufacture multiple products and process geometries in the same fabrication platform.

Incorporating SIMS Structures in Product Wafers in Order to Perform SIMS and other Material Analysis and Achieve Wafer Level Information about the Front-End Processing

In this paper, we summarize how the introduction of SIMS structures near the global alignment marks of product wafers serve as an additional way to acquire detailed analytical information about front-end processing and can minimize product yield loss without waiting for metal 1 processing when electrical testing (ET) becomes possible

Applications of SIMS supporting front- and back-end process characterization to achieve electrically matched devices

Application of SIMS metrology in high volume wafer manufacturing allows comparison of important physical characteristics of devices and can address changes in the process during early stages of process flow, thus improving production cycle. In the current paper, we investigate the correlation between wafer-level SIMS characterization and electrical characteristics of devices in a wide spectrum of front- and back-end applications: 1) High precision SIMS analysis for implanter recipe development and monitoring is a technique that has provided major contributions to achieve electrically matched devices. SIMS analysis is also used widely on gate material selection and characterization. As SiGe/SiGeC is taking precedence over III-V materials for RF applications due to processing simplicity, SIMS analytical technique provides major metrology support on process targeting and development. 2) Fluorine SIMS analysis investigation in TiN, W and its relation with increased via resistance and voids on the nucleation is an example of SIMS analysis application for back-end process support.