Craig Printy

CBC8: A 0.25 µm SiGe-CBiCMOS technology platform on thick-film SOI for high-performance analog and RF IC design

A production released complementary-SiGe BiCMOS technology on SOI has been developed for high speed analog and RFIC applications. It features matched SiGe:C PNP and NPN transistors. The PNP shows cutting edge performance metrics with β·VA =17,000 and near record fT·BVCEO ≥ 195GHz·V for a 5V process while demonstrating best in class linearity on a fully differential amplifier design. A modular process flow was leveraged to enhance the Analog design needs for the platform. For higher-speed lower power, we also demonstrate a low voltage SiGe NPN with peak fT of 50 GHz at low-bias (VCE = 0.5V), ideal for load line drive. Finally, we discuss core CMOS devices which utilize a dual-gate oxide process for improved mixed-signal mixed-voltage design and better optimization of digital blocks.

Developing a High Volume Manufacturing Wet Clean Process to Remove BF2 Implant Induced Molybdenum Contamination

This work details the investigation of potential problems in Complimentary BiCMOS technology, especially PNP transistors arrays. Optical examination of the wafer revealed defects in the P Buried Layer (PBL) areas of the die. Electrical testing correlated these PBL defects to PNP array current leakage. As the PBL module is completed very early on in the process, we devised a shortloop (SL) to reproduce these defects and identify the root cause of current leakage.

Effects of Boron and Germanium Base Profiles on SiGe and SiGe:C BJT Characteristics

We present results of an experiment with different boron and germanium profiles aimed at the optimization of the vertical profile in SiGe BJT. Simulation and experimental results show the importance of correct positioning of the germanium profile relative to boron profile to achieve maximum fTpeak. Introduction of the low-doped base region at the emitter side if well optimized improves the base current ideality and low-current fT without fTpeak reduction.

Developing a high volume manufacturing method to eliminate P Buried Layer implant defects

Atomic Force Microscopy, Deep Level Transient Spectroscopy and Secondary Ion Mass Spectroscopy were used to study defects created in the P Buried Layer while using a BF2 implant. The P Buried Layer defects were traced to the unintentional co-implantation of Mo along with the BF2 implant. Using a Tungsten source, instead of a Molybdenum source for the BF2 implant, reduced but did not eliminate these defects. A novel, high volume processing method was developed to produce metal contamination-free buried layers and verified by deep level transient spectroscopy spectra.

Incorporating SIMS Structures in Product Wafers in Order to Perform SIMS and other Material Analysis and Achieve Wafer Level Information about the Front-End Processing

In this paper, we summarize how the introduction of SIMS structures near the global alignment marks of product wafers serve as an additional way to acquire detailed analytical information about front-end processing and can minimize product yield loss without waiting for metal 1 processing when electrical testing (ET) becomes possible

In-line metrology methods for manufacturing control of BiCMOS films

This paper describes the methodologies used for manufacturing control of BiCMOS layer processing in the ASM Epsilon reactor at National Semiconductors 200 mm wafer fab in South Portland Maine. Real time monitoring techniques have been developed to control collector epi slip, SiGe layer thickness, Ge concentration and As concentration. These monitors provide objective and low cost monitoring for epi manufacturing processes.