Themistoklis Prodromakis

Integration of nanoscale memristor synapses in neuromorphic computing architectures

Conventional neuro-computing architectures and artificial neural networks have often been developed with no or loose connections to neuroscience. As a consequence, they have largely ignored key features of biological neural processing systems, such as their extremely low-power consumption features or their ability to carry out robust and efficient computation using massively parallel arrays of limited precision, highly variable, and unreliable components. Recent developments in nano-technologies are making available extremely compact and low power, but also variable and unreliable solid-state devices that can potentially extend the offerings of availing CMOS technologies. In particular, memristors are regarded as a promising solution for modeling key features of biological synapses due to their nanoscale dimensions, their capacity to store multiple bits of information per element and the low energy required to write distinct states. In this paper, we first review the neuro- and neuromorphic computing approaches that can best exploit the properties of memristor and scale devices, and then propose a novel hybrid memristor-CMOS neuromorphic circuit which represents a radical departure from conventional neuro-computing approaches, as it uses memristors to directly emulate the biophysics and temporal dynamics of real synapses. We point out the differences between the use of memristors in conventional neuro-computing architectures and the hybrid memristor-CMOS circuit proposed, and argue how this circuit represents an ideal building block for implementing brain-inspired probabilistic computing paradigms that are robust to variability and fault tolerant by design.

A Versatile Memristor Model With Nonlinear Dopant Kinetics

The need for reliable models that take into account the nonlinear kinetics of dopants is nowadays of paramount importance, particularly with the physical dimensions of electron devices shrinking to the deep nanoscale range and the development of emerging nanoionic systems such as the memristor. In this paper, we present a novel nonlinear dopant drift model that resolves the boundary issues existing in previously reported models that can be easily adjusted to match the dynamics of distinct memristive elements. With the aid of this model, we examine switching mechanisms, current-voltage characteristics, and the collective ion transport in two terminal memristive devices, providing new insights on memristive behavior.

STDP and STDP variations with memristors for spiking neuromorphic learning systems

In this paper we review several ways of realizing asynchronous Spike-Timing-Dependent-Plasticity (STDP) using memristors as synapses. Our focus is on how to use individual memristors to implement synaptic weight multiplications, in a way such that it is not necessary to (a) introduce global synchronization and (b) to separate memristor learning phases from memristor performing phases. In the approaches described, neurons fire spikes asynchronously when they wish and memristive synapses perform computation and learn at their own pace, as it happens in biological neural systems. We distinguish between two different memristor physics, depending on whether they respond to the original “moving wall” or to the “filament creation and annihilation” models. Independent of the memristor physics, we discuss two different types of STDP rules that can be implemented with memristors: either the pure timing-based rule that takes into account the arrival time of the spikes from the pre- and the post-synaptic neurons, or a hybrid rule that takes into account only the timing of pre-synaptic spikes and the membrane potential and other state variables of the post-synaptic neuron. We show how to implement these rules in cross-bar architectures that comprise massive arrays of memristors, and we discuss applications for artificial vision.

Two centuries of memristors

Memristors are dynamic electronic devices whose nanoscale realization has led to considerable research interest. However, their experimental history goes back two centuries.

The effect of microgrooved culture substrates on calcium cycling of cardiac myocytes derived from human induced pluripotent stem cells

Induced pluripotent stem cell-derived cardiomyocytes (iPSC-CM) have been widely proposed as in vitro models of myocardial physiology and disease. A significant obstacle, however, is their immature phenotype. We hypothesised that Ca2+ cycling of iPSC-CM is influenced by culture conditions and can be manipulated to obtain a more mature cellular behaviour. To test this hypothesis we seeded iPSC-CM onto fibronectin coated microgrooved polydimethylsiloxane (PDMS) scaffolds fabricated using photolithography, or onto unstructured PDMS membrane. After two weeks in culture, the structure and function of iPSC-CM were studied. PDMS microgrooved culture substrates brought about cellular alignment (p < 0.0001) and more organised sarcomere. The Ca2+ cycling properties of iPSC-CM cultured on these substrates were significantly altered with a shorter time to peak amplitude (p = 0.0002 at 1 Hz), and more organised sarcoplasmic reticulum (SR) Ca2+ release in response to caffeine (p < 0.0001), suggesting improved SR Ca2+ cycling. These changes were not associated with modifications in gene expression. Whilst structured tissue culture may make iPSC-CM more representative of adult myocardium, further construct development and characterisation is required to optimise iPSC-CM as a model of adult myocardium.

Memory Impedance in TiO2 based Metal-Insulator-Metal Devices

Large attention has recently been given to a novel technology named memristor, for having the potential of becoming the new electronic device standard. Yet, its manifestation as the fourth missing element is rather controversial among scientists. Here we demonstrate that TiO2-based metal-insulator-metal devices are more than just a memory-resistor. They possess resistive, capacitive and inductive components that can concurrently be programmed; essentially exhibiting a convolution of memristive, memcapacitive and meminductive effects. We show how non-zero crossing current-voltage hysteresis loops can appear and we experimentally demonstrate their frequency response as memcapacitive and meminductive effects become dominant.

Emulating short-term synaptic dynamics with memristive devices

Neuromorphic architectures offer great promise for achieving computation capacities beyond conventional Von Neumann machines. The essential elements for achieving this vision are highly scalable synaptic mimics that do not undermine biological fidelity. Here we demonstrate that single solid-state TiO2 memristors can exhibit non-associative plasticity phenomena observed in biological synapses, supported by their metastable memory state transition properties. We show that, contrary to conventional uses of solid-state memory, the existence of rate-limiting volatility is a key feature for capturing short-term synaptic dynamics. We also show how the temporal dynamics of our prototypes can be exploited to implement spatio-temporal computation, demonstrating the memristors full potential for building biophysically realistic neural processing systems.

Real-time encoding and compression of neuronal spikes by metal-oxide memristors

Advanced brain-chip interfaces with numerous recording sites bear great potential for investigation of neuroprosthetic applications. The bottleneck towards achieving an efficient bio-electronic link is the real-time processing of neuronal signals, which imposes excessive requirements on bandwidth, energy and computation capacity. Here we present a unique concept where the intrinsic properties of memristive devices are exploited to compress information on neural spikes in real-time. We demonstrate that the inherent voltage thresholds of metal-oxide memristors can be used for discriminating recorded spiking events from background activity and without resorting to computationally heavy off-line processing. We prove that information on spike amplitude and frequency can be transduced and stored in single devices as non-volatile resistive state transitions. Finally, we show that a memristive device array allows for efficient data compression of signals recorded by a multi-electrode array, demonstrating the technologys potential for building scalable, yet energy-efficient on-node processors for brain-chip interfaces.

Resistive switching of oxygen enhanced TiO2 thin-film devices

In this work, we investigate the effect of oxygen-enhanced TiO2 thin films on the switching dynamics of Pt/TiO2/Pt memristive nanodevices. We demonstrate that such devices can be used as resistive random access memory (RRAM) cells without required electroforming. We experimentally demonstrate that devices based on TiO2 films fabricated via sputtering with partial pressures of Ar/O2 6/6 sccm and 2/10 sccm show OFF/ON ratios of six and two orders of magnitude, respectively. Additionally, it was found that a lower O2 flow during sputtering of TiO2 allows for lower energy requirements for switching the devices from a high to low resistive state.

A Proposal for Hybrid Memristor-CMOS Spiking Neuromorphic Learning Systems

Recent research in nanotechnology has led to the practical realization of nanoscale devices that behave as memristors, a device that was postulated in the seventies by Chua based on circuit theoretical reasonings. On the other hand, neuromorphic engineering, a discipline that implements physical artifacts based on neuroscience knowledge, has related neural learning mechanisms to the operation of memristors. As a result, neuro-inspired learning architectures can be proposed that exploit nanoscale memristors for building very large scale systems with very dense synaptic-like memory elements. At present, the deep understanding of the internal mechanisms governing memristor operation is still an open issue, and the practical realization of very large scale and reliable ?memristive fabric? for neural learning applications is not a reality yet. However, in the meantime, researchers are proposing and analyzing potential circuit architectures that would combine a standard CMOS substrate with a memristive nanoscale fabric on top to realize hybrid memristor-CMOS neural learning systems. The focus of this paper is on one such architecture for implementing the very well established Spike-Timing-Dependent-Plasticity (STDP) learning mechanism found in biology. In this paper we quickly review spiking neural systems, STDP learning, and memristors, and propose a hybrid memristor-CMOS system architecture with the potential of implementing a large scale STDP learning spiking neural system. Such architecture would eventually allow to implement real-time brain-like processing learning systems with about neurons and synapses on one single Printed Circuit Board (PCB).