R. Bouyssou

Scatterometric porosimetry: A new characterization technique for porous material patterned structures

A new technique, so called “scatterometric porosimetry” (SP) has been developed to improve our knowledge on the properties of porous material patterned structures. None of the existing techniques is able to characterize the porous material structures after patterning. SP is based on the measurement of the refractive index variation of porous material structures (lines and holes) when filled with a solvent (toluene, methanol, and water). This technique is applied to monitor the modifications in low-K dielectric materials (porous SiOCH) after the plasma patterning steps used to form lines and vias in the porous materials in a typical dual damascene CMOS technology process.

Patterning of porous SiOCH using an organic mask: Comparison with a metallic masking strategy

The etching of sub-100-nm porous dielectric trenches has been investigated using an organic mask. The etching process that is performed in an oxide etcher is composed of three steps: a thin dielectric antireflective coating (DARC) layer (silicon containing layer) is etched in the first step, the organic mask [carbon-based layer (CL)] is opened in the second step, and the dielectric layer is etched in the last step. The DARC layer is open in a fluorocarbon-based plasma (CF4∕Ar∕CH2F2) and the main critical dimension issue is the critical dimension control of the trench, which can be adjusted by controlling the amount of polymer generated by the etching chemistry (% of CH2F2). The CL is etched using NH3 based plasmas, leading to straight trench profiles. For dielectric patterning, the etch process results from a delicate trade-off between passivation layer thickness and mask faceting. This is driven by the polymerizing rate of the plasma (% of CH2F2) which controls the trench width. Using an optimized etchin...

Data fusion for CD metrology: heterogeneous hybridization of scatterometry, CDSEM, and AFM data

The manufacturing of next generation semiconductor devices forces metrology tool providers for an exceptional effort in order to meet the requirements for precision, accuracy and throughput stated in the ITRS. In the past years hybrid metrology (based on data fusion theories) has been investigated as a new methodology for advanced metrology [1][2][3]. This paper provides a new point of view of data fusion for metrology through some experiments and simulations. The techniques are presented concretely in terms of equations to be solved. The first point of view is High Level Fusion which is the use of simple numbers with their associated uncertainty postprocessed by tools. In this paper, it is divided into two stages: one for calibration to reach accuracy, the second to reach precision thanks to Bayesian Fusion. From our perspective, the first stage is mandatory before applying the second stage which is commonly presented [1]. However a reference metrology system is necessary for this fusion. So, precision can be improved if and only if the tools to be fused are perfectly matched at least for some parameters. We provide a methodology similar to a multidimensional TMU able to perform this matching exercise. It is demonstrated on a 28 nm node backend lithography case. The second point of view is Deep Level Fusion which works on the contrary with raw data and their combination. In the approach presented here, the analysis of each raw data is based on a parametric model and connections between the parameters of each tool. In order to allow OCD/SEM Deep Level Fusion, a SEM Compact Model derived from [4] has been developed and compared to AFM. As far as we know, this is the first time such techniques have been coupled at Deep Level. A numerical study on the case of a simple stack for lithography is performed. We show strict equivalence of Deep Level Fusion and High Level Fusion when tools are sensitive and models are perfect. When one of the tools can be considered as a reference and the second is biased, High Level Fusion is far superior to standard Deep Level Fusion. Otherwise, only the second stage of High Level Fusion is possible (Bayesian Fusion) and do not provide substantial advantage. Finally, when OCD is equipped with methods for bias detection [5], Deep Level Fusion outclasses the two-stage High Level Fusion and will benefit to the industry for most advanced nodes production.

Patterning critical dimension control for advanced logic nodes

Abstract. Patterning process control has undergone major evolutions over the last few years. Critical dimension, focus, and overlay control require deep insight into process-variability understanding to be properly apprehended. Process setup is a complex engineering challenge. In the era of mid k1 lithography (>0.6), process windows were quite comfortable with respect to tool capabilities, therefore, some sources of variability were, if not ignored, at least considered as negligible. The low k1 patterning (<0.4) era has broken down this concept. For the most advanced nodes, engineers need to consider such a wide set of information that holistic processing is often mentioned as the way to handle the setup of the process and its variability. The main difficulty is to break down process-variability sources in detail and be aware that what could have been formerly negligible has become a very significant contributor requiring control down to a fraction of a nanometer. The scope of this article is to highlight that today, engineers have to zoom deeper into variability. Even though process tools have greatly improved their capabilities, diminishing process windows require more than tool-intrinsic optimization. Process control and variability compensations are major contributors to success. Some examples will be used to explain how complex the situation is and how interlinked processes are today.

Scatterometric Porosimetry for porous low-k patterns characterization

Porous low-k dielectrics integration in interconnects is required to keep improving Integrated Circuits performance. However, these materials are highly sensitive to plasma processes and may be damaged during the patterning steps. Characterizing the plasma induced modification is required on patterned structures to develop less damaging plasma processes. Scatterometric Porosimetry (SP) has recently been introduced to characterize the plasma-induced porous low-k modification on patterned structures. By discussing the sensitivity and correlations of the different optimization parameters on a simple dielectric stack, we will show in which manner the SP method is applicable to fundamental studies and to process optimization.

Impact of ambient atmosphere on plasma-damaged porous low-k characterization

Improving Integrated Circuits performance requires the use of porous SiCOH in interconnects. However, porosity leads to plasma species diffusion into the material during the patterning steps, which damages the low-k properties. Characterizing plasma-damaged porous SiCOH is not straightforward, and requires a specific characterization setup and protocol. In this paper, we show the impact of the ambient atmosphere on the low-k properties, and how it should be taken into account during the characterization of plasma-damaged porous SiCOH.

Development of Porosimetry Techniques for the Characterization of Plasma-Treated Porous Ultra Low-K Materials

Introduction Down-scaling of complementary metal oxide semiconductor (CMOS) devices requires the integration of copper/porous ultra low-k (ULK) materials to reduce the interconnect resistance-capacitance delay. For the sub32 nm nodes, porous SiCOH dielectrics (p-SiCOH) are integrated using the dual damascene patterning by etching trenches and vias into the porous material. Fig. 1 shows an example of ULK integration using the metallic hard mask strategy. Since the pore structure leads to higher sensitivity of the material to environmental and process conditions, controlling the profiles of the etched structures and minimizing the plasma-induced damage of p-SiCOH materials are the two main challenges. The sensitive areas are the bottom and the sidewall of the trenches where surface modifications, post-etch residues, or p-SiCOH roughening can occur.

Etching process scalability and challenges for ULK materials

With the scaling down of integrated circuit devices, a constant effort is needed to improve the patterning technologies of interconnect stacks using either the metallic masking strategy or the organic masking strategy. Critical dimensions and profile control, plasma-induced damages (modifications, post etch residues, porous SiOCH roughening) are the key challenges to successfully pattern dual damascene porous SiOCH structures. We have compared the patterning performances of both masking strategies in terms of profile control. One of the main challenges is to optimize the plasma processes to minimize the dielectric sidewall modification. This has been achieved by using optimized or new characterization techniques such as scatterometric porosimetry, infrared spectroscopy, x-ray photoelectron spectroscopy.

Study of µDBO overlay target size reduction for application broadening

With these proceedings we present μ-diffraction-based overlay (μDBO) targets that are well below the currently supported minimum size of 10×10 μm2 . We have been capable of measuring overlay targets as small as 4×4 μm2 with our latest generation YieldStar system. Furthermore we find an excellent precision (TMU < 0.33 nm for 6 × 6 μm2 ) without any compromise on throughput (MAM time < 60 ms). At last a study that compares four generations of YieldStar systems show clearly that the latest generation YieldStar systems is much better capable of reading small overlay targets such that the performance of a 16 × 16 μm2 on an early generation YieldStar 2nd-gen is comparable to that of a 8 × 8 μm2 on the latest YieldStar 5th-gen. This work enables a smaller metrology footprint, more placement flexibility and in-die overlay metrology solutions.

Image based overlay measurement improvements of 28nm FD-SOI CMOS front-end critical steps

Technology shrinkage leads to tight specifications in advanced semiconductor industries. For several years’, metrology for lithography has been a key technology to address this challenge and to improve yield. More specifically overlay metrology is the object of special attention for tool suppliers and semiconductor manufacturers. This work focuses on Image Based Overlay (IBO) metrology for 28 nm FD-SOI CMOS front-end critical steps (gate and contact). With Overlay specifications below 10 nm, accuracy of the measurement is critical. In this study we show specific cases where target designs need to be optimized in order to minimize process effects (CMP, etch, deposition, etc.) that could lead to overlay measurement errors. Another important aspect of the metrology target is that its design must be device-like in order to better control and correct overlay errors leading to yield loss. Methodologies to optimize overlay metrology recipes are also presented. If the process effects cannot be removed entirely by target design optimization, recipe parameters have to be carefully chosen and controlled to minimize the influence of the target imperfection on measured overlay. With target asymmetry being one of the main contributors to those residual overlay measurement errors the Qmerit accuracy flag can be used to quantify the measurement error and recipe parameters can be set accordingly in order to minimize the target asymmetry impact. Reference technique measurements (CD-SEM) were used to check accuracy of the optimized overlay measurements.