Thierry Pinguet

A Grating-Coupler-Enabled CMOS Photonics Platform

We have developed a silicon photonics platform that allows monolithic integration with electronic circuits in a CMOS-compatible process. In this platform, vertical couplers are found to be a superior solution compared to traditional edge-coupling techniques. Grating couplers are an essential element in developing the optical wafer-scale test infrastructure, which in turn, enables the development of the photonic device library. The photonic devices were assembled into a 4 × 10 Gb/s transceiver die that also contains modulator drive, control, and receive electronics.

Ultra-efficient 10Gb/s hybrid integrated silicon photonic transmitter and receiver

Using low parasitic microsolder bumping, we hybrid integrated efficient photonic devices from different platforms with advanced 40 nm CMOS VLSI circuits to build ultra-low power silicon photonic transmitters and receivers for potential applications in high performance inter/intra-chip interconnects. We used a depletion racetrack ring modulator with improved electro-optic efficiency to allow stepper optical photo lithography for reduced fabrication complexity. Integrated with a low power cascode 2 V CMOS driver, the hybrid silicon photonic transmitter achieved better than 7 dB extinction ratio for 10 Gbps operation with a record low power consumption of 1.35 mW. A received power penalty of about 1 dB was measured for a BER of 10(-12) compared to an off-the-shelf lightwave LiNOb3 transmitter, which comes mostly from the non-perfect extinction ratio. Similarly, a Ge waveguide detector fabricated using 130 nm SOI CMOS process was integrated with low power VLSI circuits using hybrid bonding. The all CMOS hybrid silicon photonic receiver achieved sensitivity of -17 dBm for a BER of 10(-12) at 10 Gbps, consuming an ultra-low power of 3.95 mW (or 395 fJ/bit in energy efficiency). The scalable hybrid integration enables continued photonic device improvements by leveraging advanced CMOS technologies with maximum flexibility, which is critical for developing ultra-low power high performance photonic interconnects for future computing systems.

Exploiting CMOS Manufacturing to Reduce Tuning Requirements for Resonant Optical Devices

We present manufacturing tolerances of cascaded silicon microring resonators fabricated in a commercial 130-nm complementary-oxide semiconductor (CMOS) foundry using 193-nm lithography and provide statistics gathered from over 500 four-channel microring arrays over multiple wafers and fabrication lots. We quantify intrawafer and interwafer variation of the position and relative spacing of resonance wavelengths for the microring arrays and confirm prior predictions that the absolute resonance positions of such devices cannot be controlled across wafers or even across reticles within a wafer. However, we show that the free spectral range (FSR) of the microrings can be controlled to within 0.66 nm (83 GHz) across wafers and lots, as can the wavelength spacing between closely spaced microrings. To exploit these findings for low-power optical interconnects, we suggest and demonstrate a synthetic resonant comb with FSR ≈ N * δλ, wherein resonance wavelengths are spaced equally across the FSR in order to minimize postfabrication tuning. The experimental CMOS 1 × 8 microring array requires an average tuning of less than 1.2 nm/channel to align to a 200-GHz wavelength division multiplexing (WDM) grid. Monte Carlo simulations on 100 000 sample runs show that an average tuning of 1.72 nm/channel is sufficient for 99% coverage for this component. This indicates that it is possible, with high statistical confidence, to use high-volume CMOS manufacturing to reduce the tuning range and tuning energy requirements of silicon microrings and, hence, enhance their ability to be used in high-density, energy-efficient computing system applications.

Highly-efficient thermally-tuned resonant optical filters

We demonstrate spectral tunability for microphotonic add-drop filters manufactured as ring resonators in a commercial 130 nm SOI CMOS technology. The filters are provisioned with integrated heaters built in CMOS for thermal tuning. Their thermal impedance has been dramatically increased by the selective removal of the SOI handler substrate under the device footprint using a bulk silicon micromachining process. An overall ~20x increase in the tuning efficiency has been demonstrated with a 100 µm radius ring as compared to a pre-micromachined device. A total of 3.9 mW of applied tuning power shifts the filter resonant peak across one free spectral node of the device. The Q-factor of the resonator remains unchanged after the co-integration process and hence this device geometry proves to be fully CMOS compatible. Additionally, after the cointegration process our result of 2π shift with 3.9 mW power is among the best tuning performances for this class of devices. Finally, we examine scaling the tuning efficiency versus device footprint to develop a different performance criterion for an easier comparison to evaluate thermal tuning. Our criterion is defined as the unit of power to shift the device resonance by a full 2π phase shift.

Ultra-low-energy all-CMOS modulator integrated with driver

We report the first sub-picojoule per bit (400fJ/bit) operation of a silicon modulator intimately integrated with a driver circuit and embedded in a clocked digital transmitter. We show a wall-plug power efficiency below 400microW/Gbps for a 130nm SOI CMOS carrier-depletion ring modulator flip-chip integrated to a 90nm bulk Si CMOS driver circuit. We also demonstrate stable error-free transmission of over 1.5 petabits of data at 5Gbps over 3.5 days using the integrated modulator without closed-loop ring resonance tuning. Small signal measurements of the CMOS ring modulator, sans circuit, showed a 3dB bandwidth in excess of 15GHz at 1V of reverse bias, indicating that further increases in transmission rate and reductions of energy-per-bit is possible while retaining compatibility with CMOS drive voltages.

Progress in Low-Power Switched Optical Interconnects

Optical links have successfully displaced electrical links when their aggregated bandwidth-distance product exceeds ~100 Gb/s-m because their link energy per bit per unit distance is lower. Optical links will continue to be adopted at distances of 1 m and below if link power falls below 1 pJ/bit/m. Providing optical links directly to a switching/routing chip can significantly improve the switched energy/bit. We present an early experimental switched CMOS-vertical-cavity surface-emitting laser (VCSEL) system operating at Gigabit Ethernet line rates that achieves a switched interconnect energy of less than 19 pJ/bit for a fully nonblocking network with 16 ports and an aggregate capacity of 20 Gb/s/port. The CMOS-VCSEL switch achieves an optical bandwidth density of 37 Gb/s/mm2 even when operating at a modest line rate of 1.25 Gb/s and is capable of scaling to much higher peak bandwidth densities (~350 Gb/s/mm2) with 5-10 pJ/switched bit. We also review a silicon photonic system design that will lower link energies to 300 fJ/bit, while providing multiterabits per second per square millimeter bandwidth densities. This system will ultimately provide switched optical interconnect at less than a picojoule per switched bit and computer/router system energies of tens of picojoule per bit. We review progress made to date on the silicon photonic components and analyze an energy and bandwidth-density roadmap for future advances toward these goals.

A tunable 1x4 silicon CMOS photonic wavelength multiplexer/demultiplexer for dense optical interconnects

We report the first compact silicon CMOS 1x4 tunable multiplexer/ demultiplexer using cascaded silicon photonic ring-resonator based add/drop filters with a radius of 12 microm, and integrated doped-resistor thermal tuners. We measured an insertion loss of less than 1 dB, a channel isolation of better than 16 dB for a channel spacing of 200 GHz, and a uniform 3 dB pass band larger than 0.4 nm across all four channels. We demonstrated accurate channel alignment to WDM ITU grid wavelengths using integrated silicon heaters with a tuning efficiency of 90 pm/mW. Using this device in a 10 Gbps data link, we observed a low power penalty of 0.6 dB.

A sub-picojoule-per-bit CMOS photonic receiver for densely integrated systems

We report ultra-low-power (690fJ/bit) operation of an optical receiver consisting of a germanium-silicon waveguide detector intimately integrated with a receiver circuit and embedded in a clocked digital receiver. We show a wall-plug power efficiency of 690microW/Gbps for the photonic receiver made of a 130nm SOI CMOS Ge waveguide detector integrated to a 90nm Si CMOS receiver circuit. The hybrid CMOS photonic receiver achieved a sensitivity of -18.9dBm at 5Gbps for BER of 10(-12). Enabled by a unique low-overhead bias refresh scheme, the receiver operates without the need for DC balanced transmission. Small signal measurements of the CMOS Ge waveguide detector showed a 3dB bandwidth of 10GHz at 1V of reverse bias, indicating that further increases in transmission rate and reductions of energy-per-bit will be possible.

Monolithically integrated high-speed CMOS photonic transceivers

We demonstrate monolithically integrated 4×10 Gb/s WDM transceivers built in a production 130 nm SOI CMOS process. Only light sources are external to the chip. 40 Gb/s error-free, bidirectional transmission is demonstrated.

A Fully Integrated 4

Optical and electronic building blocks required for DWDM transceivers have been integrated in a 0.13 mum CMOS SOI technology. Using these building blocks, a 4 x 10-Gb/s single-chip DWDM optoelectronic transceiver with 200 GHz channel spacing has been demonstrated. The DWDM transceiver demonstrates an unprecedented level of optoelectronic system integration, bringing all required optical and electronic transceiver functions together on a single SOI substrate. An aggregate data rate of 40 Gb/s was achieved over a single fiber, with a BER of less than 10-12 and a power consumption of 3.5 W.