Christopher W. Leitz

Controlling threading dislocation densities in Ge on Si using graded SiGe layers and chemical-mechanical polishing

A method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented. This method has allowed us to grow a relaxed graded buffer to 100% Ge without the increase in threading dislocation density normally observed in thick graded structures. This sample has been characterized by transmission electron microscopy, etch-pit density, atomic force microscopy, Nomarski optical microscopy, and triple-axis x-ray diffraction. Compared to other relaxed graded buffers in which CMP was not implemented, this sample exhibits improvements in threading dislocation density and surface roughness. We have also made process modifications in order to eliminate particles due to gas-phase nucleation and cracks due to thermal mismatch strain. We have achieved relaxed Ge on Si with a threading dislocation density of 2.1×106 cm−2, and we expect that further process refinements will lead to lower threading dislocation densities on the order of bulk Ge su...

Strained Ge channel p-type metal–oxide–semiconductor field-effect transistors grown on Si1−xGex/Si virtual substrates

We have fabricated strained Ge channel p-type metal–oxide–semiconductor field-effect transistors (p-MOSFETs) on Si0.3Ge0.7 virtual substrates. The poor interface between silicon dioxide (SiO2) and the Ge channel was eliminated by capping the strained Ge layer with a relaxed, epitaxial silicon surface layer grown at 400 °C. Ge p-MOSFETs fabricated from this structure show a hole mobility enhancement of nearly eight times that of co-processed bulk Si devices, and the Ge MOSFETs have a peak effective mobility of 1160 cm2/V s. These MOSFETs demonstrate the possibility of creating a surface channel enhancement-mode MOSFET with buried channel-like transport characteristics.

High quality Ge on Si by epitaxial necking

We show that pure Ge grown selectively on SiO2/Si substrates in 100 nm holes is highly perfect at the top surface compared to conventional Ge lattice-mismatched growth on planar Si substrates. This result is achieved through a combination of interferometric lithography SiO2/Si substrate patterning and ultrahigh vacuum chemical vapor deposition Ge selective epitaxial growth. This “epitaxial necking,” in which threading dislocations are blocked at oxide sidewalls, shows promise for dislocation filtering and the fabrication of low-defect density Ge on Si. Defects at the Ge film surface only arise at the merging of epitaxial lateral overgrowth fronts from neighboring holes. These results confirm that epitaxial necking can be used to reduce threading dislocation density in lattice-mismatched systems.

Monolithic integration of room-temperature cw GaAs/AlGaAs lasers on Si substrates via relaxed graded GeSi buffer layers

GaAs/AlxGa(1−x)As quantum well lasers have been demonstrated via organometallic chemical vapor deposition on relaxed graded Ge/GexSi(1−x) virtual substrates on Si. A number of GaAs/Ge/Si integration issues including Ge autodoping behavior in GaAs, reduced critical thickness due to thermal expansion mismatch, and complications with mirror facet cleaving have been overcome. Despite unoptimized laser structures with high series resistance and large threshold current densities, surface threading dislocation densities for GaAs/AlGaAs lasers on Si substrates as low as 2×106 cm−2 permitted continuous room-temperature lasing at a wavelength of 858 nm. The laser structures are uncoated edge-emitting broad-area devices with differential quantum efficiencies of 0.24 and threshold current densities of 577 A/cm2. Identical devices grown on commercial GaAs substrates showed similar behavior. This comparative data agrees with previous measurements of near-bulk minority carrier lifetimes in GaAs grown on Ge/GeSi/Si subst...

Hole mobility enhancements in strained Si/Si1-yGey p-type metal-oxide-semiconductor field-effect transistors grown on relaxed Si1-xGex (x<y) virtual substrates

We have achieved peak hole mobility enhancement factors of 5.15 over bulk Si in metal-oxide-semiconductor field-effect transistors (MOSFETs) by combining tensile strained Si surface channels and compressively strained 80% Ge buried channels grown on relaxed 50% Ge virtual substrates. To further investigate hole transport in these dual channel structures, we study the effects of strain, alloy scattering, and layer thickness on hole mobility enhancements in MOSFETs based upon these layers. We show that significant performance boosts can be obtained despite the effects of alloy scattering and that the best hole mobility enhancements are obtained for structures with thin Si surface layers.

Hole mobility enhancements and alloy scattering-limited mobility in tensile strained Si/SiGe surface channel metal–oxide–semiconductor field-effect transistors

Strained Si-based metal–oxide–semiconductor field-effect transistors (MOSFETs) are promising candidates for next-generation complementary MOS (CMOS) technology. While electron mobility enhancements in these heterostructures have been thoroughly investigated, hole mobility enhancements have not been explored in as much detail. In this study, we investigate the dependence of hole mobility in strained Si MOSFETs on substrate Ge content, strained layer thickness, and channel composition. We show that hole mobility enhancements saturate at virtual substrate compositions of 40% Ge and above, with peak mobility enhancements over twice that of coprocessed bulk Si devices. These results represent peak hole mobilities above 200cm2/V-S. Furthermore, we demonstrate that hole mobility in strained Si/relaxed Si0.7Ge0.3 heterostructures displays no strong dependence on strained layer thickness, indicating that strain is the primary variable controlling channel mobility in strained Si p-type MOSFETs (p-MOSFETs). We then ...

Dislocation glide and blocking kinetics in compositionally graded SiGe/Si

The effects of growth temperature, substrate offcut, and dislocation pileup formation on threading dislocation density (TDD) in compositionally graded SiGe buffers are explored. To investigate dislocation glide kinetics in these structures, a series of identical samples graded to 30% Ge were grown at temperatures between 650 and 900 °C on (001)-, (001) offcut 6° towards an in-plane 〈110〉-, and (001) offcut 6° towards an in-plane 〈100〉-oriented Si substrates. The field threading dislocation density (field TDD) in the on-axis samples varied exponentially with temperature, from 3.7×106 cm−2 at 650 °C to 9.3×104 cm−2 at 900 °C. The activation energy for dislocation glide in this series, calculated from the evolution of field TDD with growth temperature, was 1.38 eV, much lower than the expected value for this composition. This deviation indicates that strain accumulating during the grading process at low growth temperatures is forcing further dislocation nucleation, resulting in a deviation from pure glide-li...

Film thickness constraints for manufacturable strained silicon CMOS

This paper studies the effect of the strained silicon thickness on the characteristics of strained silicon MOSFETs on SiGe virtual substrates. NMOSFETs were fabricated on strained silicon substrates with various strained silicon thicknesses, both above and below the strained silicon critical thickness. The low field electron mobility and subthreshold characteristics of the devices were measured. Low field electron mobility is increased by about 1.8 times on all wafers and is not significantly degraded on any of the samples, even for a strained silicon thickness far greater than the critical thickness. From the subthreshold characteristics, however, it is shown that the off-state leakage current is greatly increased for the devices on the wafers with a strained silicon thickness that exceeds the critical thickness. The mechanism of the leakage was examined by using photon emission microscopy. Strong evidence is shown that the leakage mechanism is source/drain electrical shorting caused by enhanced dopant diffusion near misfit dislocations.

High efficiency GaAs-on-Si solar cells with high V/sub oc/ using graded GeSi buffers

Single junction AlGaAs/GaAs and InGaP/GaAs solar cells and test structures have been grown by molecular beam epitaxy (MBE) and metalorganic chemical vapor deposition (MOCVD), respectively, on Si wafers coated with compositionally-graded GeSi buffers. The combination of controlled strain relaxation within the GeSi buffer and monolayer-scale control of the Ill-V layer nucleation is shown to reproducibly generate minority carrier lifetimes exceeding 10 nanoseconds within GaAs overlayers. The III-V layers are free of long-range antiphase domain disorder, with threading dislocation densities in the high-10/sup 5/ cm/sup -2/ range, consistent with the low residual dislocation density in the Ge cap of the graded buffer structure. Single junction GaAs cells grown by both MBE and MOCVD on the Ge/GeSi/Si substrates demonstrated high V/sub oc/ values for GaAs cells grown on Si. Record V/sub oc/ values for MOCVD-grown single junction InGaP/GaAs cells exceeded 980 mV (AMO) with fill factors of 0.79. Additionally, external quantum efficiency data indicates no degradation in carrier collection from GaAs homoepitaxial cells for current single-junction cell designs grown by MBE. Based on these results, cell efficiencies in excess of 18.5% under AM0 conditions should be attainable with cell designs demonstrating state of the art J/sub sc/ values. Such cell performance demonstrates the potential and viability of graded GeSi buffers for the development of Ill-V cells on Si wafers.

Dislocations in Relaxed SiGe/Si Heterostructures

Recent advances in the understanding and control of threading dislocations in substantially relaxed SiGe buffer layers on Si are presented. A model for threading dislocation flow in relaxed graded SiGe buffers is used to determine the potential lower limit of threading dislocation density in relaxed SiGe buffers. Greater densities than expected from the model are seen in relaxed graded alloys with final concentrations greater than 50%. We show that the culprits of the higher threading dislocation density are threading dislocation pile-ups. Observation of early development of pile-ups confirms that inhomogeneous misfit dislocation densities in the graded buffer form regions of more severe crosshatch on the surface that impede dislocation flow. By using chemomechanical planarization (CMP), deleterious pile-up formation can be avoided, and previously formed pile-ups can be destroyed by regrowth of a graded layer. Experiments with CMP and regrowth of graded layers suggest that dislocation annihilation can be effective at reducing threading dislocation densities to densities of the order expected by the model. High quality Ge on Si layers created with the CMP process were used as templates to grow high quality GaAs on Si with strong room temperature photoluminescence and record minority carrier lifetime.