Zhiyuan Cheng

Strained Ge channel p-type metal–oxide–semiconductor field-effect transistors grown on Si1−xGex/Si virtual substrates

We have fabricated strained Ge channel p-type metal–oxide–semiconductor field-effect transistors (p-MOSFETs) on Si0.3Ge0.7 virtual substrates. The poor interface between silicon dioxide (SiO2) and the Ge channel was eliminated by capping the strained Ge layer with a relaxed, epitaxial silicon surface layer grown at 400 °C. Ge p-MOSFETs fabricated from this structure show a hole mobility enhancement of nearly eight times that of co-processed bulk Si devices, and the Ge MOSFETs have a peak effective mobility of 1160 cm2/V s. These MOSFETs demonstrate the possibility of creating a surface channel enhancement-mode MOSFET with buried channel-like transport characteristics.

Electron mobility enhancement in strained-Si n-MOSFETs fabricated on SiGe-on-insulator (SGOI) substrates

We demonstrate electron mobility enhancement in strained-Si n-MOSFETs fabricated on relaxed Si/sub 1-x/Ge/sub x/-on-insulator (SGOI) substrates with a high Ge content of 25%. The substrates were fabricated by wafer bonding and etch-back utilizing a 20% Ge layer as an etch stop. Epitaxial regrowth was used to produce the upper portion of the Si/sub 0.75/Ge/sub 0.26/ and the surface strained Si layer. Large-area strained-Si n-MOSFETs were fabricated on this SGOI substrate. The measured electron mobility shows significant enhancement over both the universal mobility and that of co-processed bulk-Si MOSFETs. This SGOI process has a low thermal budget and thus is compatible with a wide range of Ge contents in Si/sub 1-x/Ge/sub x/ layer.

Hole mobility enhancements in strained Si/Si1-yGey p-type metal-oxide-semiconductor field-effect transistors grown on relaxed Si1-xGex (x<y) virtual substrates

We have achieved peak hole mobility enhancement factors of 5.15 over bulk Si in metal-oxide-semiconductor field-effect transistors (MOSFETs) by combining tensile strained Si surface channels and compressively strained 80% Ge buried channels grown on relaxed 50% Ge virtual substrates. To further investigate hole transport in these dual channel structures, we study the effects of strain, alloy scattering, and layer thickness on hole mobility enhancements in MOSFETs based upon these layers. We show that significant performance boosts can be obtained despite the effects of alloy scattering and that the best hole mobility enhancements are obtained for structures with thin Si surface layers.

Hole mobility enhancements and alloy scattering-limited mobility in tensile strained Si/SiGe surface channel metal–oxide–semiconductor field-effect transistors

Strained Si-based metal–oxide–semiconductor field-effect transistors (MOSFETs) are promising candidates for next-generation complementary MOS (CMOS) technology. While electron mobility enhancements in these heterostructures have been thoroughly investigated, hole mobility enhancements have not been explored in as much detail. In this study, we investigate the dependence of hole mobility in strained Si MOSFETs on substrate Ge content, strained layer thickness, and channel composition. We show that hole mobility enhancements saturate at virtual substrate compositions of 40% Ge and above, with peak mobility enhancements over twice that of coprocessed bulk Si devices. These results represent peak hole mobilities above 200cm2/V-S. Furthermore, we demonstrate that hole mobility in strained Si/relaxed Si0.7Ge0.3 heterostructures displays no strong dependence on strained layer thickness, indicating that strain is the primary variable controlling channel mobility in strained Si p-type MOSFETs (p-MOSFETs). We then ...

Fully depleted n-MOSFETs on supercritical thickness strained SOI

Strained silicon-on-insulator (SSOI) is a new material system that combines the carrier transport advantages of strained Si with the reduced parasitic capacitance and improved MOSFET scalability of thin-film SOI. We demonstrate fabrication of highly uniform SiGe-free SSOI wafers with 20% Ge equivalent strain and report fully depleted n-MOSFET results. We show that enhanced mobility is maintained in strained Si films transferred directly to SiO/sub 2/ from relaxed Si/sub 0.8/Ge/sub 0.2/ virtual substrates, even after a generous MOSFET fabrication thermal budget. Further, we find the usable strained-Si thickness of SSOI significantly exceeds the critical thickness of strained Si/SiGe without deleterious leakage current effects typically associated with exceeding this limit.

Strained Ge channel p-type MOSFETs fabricated on Si1-xGex/Si virtual substrates

We have fabricated strained Ge channel p -type metal oxide semiconductor field-effect transistors ( p -MOSFETs) on Si 1−x Ge x (x=0.7 to 0.9) virtual substrates. Capping the channel with a relaxed, epitaxial silicon layer eliminates the poor interface between silicon dioxide (SiO 2 ) and pure Ge. The effects of the Si cap thickness, the strain in the Ge channel, and the thickness of the Ge channel on hole mobility enhancement were investigated. Optimized strained Ge p- MOSFETs show hole mobility enhancements of nearly 8 times that of co-processed bulk Si devices across a wide range of vertical field. These devices demonstrate that the high mobility holes in strained Ge can be utilized in a MOS device despite the need to cap the channel with a highly dislocated Si layer.

Atomic-layer-deposited Al2O3/GaAs metal-oxide-semiconductor field-effect transistor on Si substrate using aspect ratio trapping technique

High quality GaAs epilayers grown by metal-organic chemical vapor deposition are demonstrated on a SiO2-patterned silicon substrate using aspect ratio trapping technique, whereby threading dislocations from lattice mismatch are largely reduced via trapping in SiO2 trenches during growth. A depletion-mode metal-oxide-semiconductor field-effect transistor (MOSFET) is demonstrated on a n-doped GaAs channel with atomic-layer deposited Al2O3 as the gate oxide. The 10 μm gate length transistor has a maximum drain current of 88 mA/mm and a transconductance of 19 mS/mm. The surface mobility estimated from the accumulation drain current has a peak value of ∼500 cm2/Vs, which is comparable with those from previously reported depletion-mode GaAs MOSFETs epitaxially grown on semi-insulating GaAs substrates.

Coplanar Integration of Lattice-Mismatched Semiconductors with Silicon by Wafer Bonding Ge / Si1 − x Ge x / Si Virtual Substrates

We have demonstrated a general process which could be used for the integration of lattice-mismatched semiconductors onto large, Si-sized wafers by wafer bonding Ge/Si 1-x Ge x /Si virtual substrates. The challenges for implementing this procedure for large diameter Ge-on-insulator (GOI) have been identified and solved, resulting in the transfer of epitaxial Ge/SiO 2 to a Si wafer. We found that planarization of Ge virtual substrates was a key limiting factor in the transfer process. To circumvent this problem, an oxide layer was first deposited on the Ge film before planarization using a standard oxide chemical mechanical planarization process. The GOI structure was created using H 2 -induced layer exfoliation (Smartcut) and a buried Si 0.4 Ge 0/6 etch-stop layer, which was used to subsequently remove the surface damage with a hydrogen peroxide selective etch. After selective etching, the crosshatched surface morphology of the original virtual substrate was preserved with roughness of <15 nm rms as measured on a 25 X 25 μm scale and a 1 × 1 μm scale roughness of < 1.4 nm. Using an etch-stop layer, the transferred device layer thickness is defined epitaxially allowing for future fabrication of ultrathin GOI as well as III-V films directly on large-diameter Si wafers.

Monolithic Integration of GaAs/InGaAs Lasers on Virtual Ge Substrates via Aspect-Ratio Trapping

GaAs/InGaAs quantum-well lasers have been demonstrated by metallorganic chemical vapor deposition on virtual Ge substrates on Si via aspect-ratio trapping (ART) and epitaxial lateral overgrowth (ELO). Laser-structure growth is achieved in two steps: The first step is growing uncoalesced defect-free Ge stripes on a SiO 2 trench-patterned silicon substrate via ART, whereby the misfit defects originating from the Ge/Si interface are trapped by laterally confining sidewalls. Defects arising from above the SiO 2 film are reduced by using an optimized ELO process followed by chemical mechanical polishing to provide a planar Ge surface. The second step is overgrowing a GaAs/InGaAs laser structure on the virtual Ge substrate. A number of GaAs/Ge integration issues, including Ge autodoping and antiphase domain defects in GaAs, have been overcome. Despite unoptimized laser structures with high series resistance and large threshold current densities, pulsed room-temperature lasing at a wavelength of 980 nm has been demonstrated using a combination of ART and ELO. This technique is very promising for the achievement of reliable GaAs-based optoelectronic devices on Si.

SiGe-On-Insulator (SGOI): substrate preparation and MOSFET fabrication for electron mobility evaluation

Relaxed Si/sub 1-x/Ge/sub x/-on-insulator (SGOI) is a very promising technology, as it combines the benefits of two advanced technologies: the conventional SOI technology and the SiGe technology. SiGe-based devices have shown advantageous DC and RF performance using, the enhanced electronic properties associated with strain engineering and heterojunction energy barriers. SGOI is a versatile substrate that can be used to integrate various device structures, such as strained-Si and strained-SiGe FETs, and III-V optoelectronics. In this work, we have fabricated SGOI substrates via two different approaches. We also demonstrate strained-Si nMOSFET fabrication on SGOI and electron mobility enhancement is evaluated.