Thomas Clouqueur

Sensor deployment strategy for target detection

In order to monitor a region for traffic traversal, sensors can be deployed to perform collaborative target detection. Such a sensor network achieves a certain level of detection performance with an associated cost of deployment. This paper addresses this problem by proposing path exposure as a measure of the goodness of a deployment and presents an approach for sequential deployment in steps. It illustrates that the cost of deployment can be minimized to achieve the desired detection performance by appropriately choosing the number of sensors deployed in each step.

Fault tolerance in collaborative sensor networks for target detection

Collaboration in sensor networks must be fault-tolerant due to the harsh environmental conditions in which such networks can be deployed. We focus on finding algorithms for collaborative target detection that are efficient in terms of communication cost, precision, accuracy, and number of faulty sensors tolerable in the network. Two algorithms, namely, value fusion and decision fusion, are identified first. When comparing their performance and communication overhead, decision fusion is found to become superior to value fusion as the ratio of faulty sensors to fault free sensors increases. As robust data fusion requires agreement among nodes in the network, an analysis of fully distributed and hierarchical agreement is also presented. The impact of hierarchical agreement on communication cost and system failure probability is evaluated and a method for determining the number of tolerable faults is identified.

Sensor deployment strategy for detection of targets traversing a region

Sensing devices can be deployed to form a network for monitoring a region of interest. This paper investigates detection of a target traversing the region being monitored by using collaborative target detection algorithms among the sensors. The objective of the study is to develop a low cost sensor deployment strategy to meet a performance criteria. The paper defines a path exposure metric as a measure of goodness of deployment. It then gives a problem formulation for the random sensor deployment and defines cost functions that take into account the cost of single sensors and the cost of deployment. A sequential sensor deployment approach is then developed. The paper illustrates that the overall cost of deployment can be minimized to achieve the desired detection performance by appropriately choosing the number of sensors deployed in each step of the sequential deployment strategy.

Design and analysis of multiple weight linear compactors of responses containing unknown values

Occurrence of unknown values in scan chains in response to test vectors is a common phenomenon. This paper presents a method for designing matrices for linear test output compactors by using rows of multiple weights. Compared to previously proposed compactors, the method reduces the masking caused by unknowns by an order of magnitude provided that the unknowns are non-uniformally distributed among the scan chains. Also, using multiple rather than single weight compactors increases the compaction ratio and reduces the hardware overhead. The effectiveness of multiple weight compactors is demonstrated through analysis, simulations and experiments with test response from an industrial design

Efficient signature-based fault diagnosis using variable size windows

A technique for signature based diagnosis using windows of different sizes is presented. It allows one to obtain increased diagnostic information from a given test at a lower cost, without additional hardware. Existing techniques that use signature based methods are limited by occurrences of aliasing that can lead to failure in the diagnosis process. The new approach proposed in this paper uses windows of different sizes based on the distribution of faults in a circuit and reduces the probability of aliasing in a window Signature analysis can then give reliable information about failing and non-failing vectors. The effectiveness of the proposed method is evaluated by experiments conducted on ISCAS benchmark circuits. The results show that the proposed method can improve the diagnostic resolution and can reduce the cost of diagnosis.

Exposure of variable speed targets through a sensor field

In order to monitor a region for target intru- sion, sensors can be deployed to perform collaborative tar- get detection. To adequately deploy sensors, metrics need to be defined to measure the ability of a given deployment to successfully complete this task. Recently, a measure of exposure was defined to evaluate the coverage of the region by a sensor network Exposure is a versatile metric that is expected to provide a pertinent measure of the region cover- age for various scenarios. This paper develops a method to find the minimum exposure of a target traversing the region at variable speed. The paper also identijes the problem of coverage in the presence of obstacles in the region and for various target activities.

Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester

Numerous solutions have been proposed to reduce test data volume and test application time during manufacturing testing of digital devices. However, time to market challenge also requires a very efficient debug phase. Error identification in the test responses can become impractically slow in the debug phase due to large debug data, slow tester speed, and limited memory of the tester. In this paper, we investigate the problems and solutions related to using a relatively slow and limited memory tester to observe the at-speed behavior of fast circuits. Our method can identify all errors in at-speed scan BIST environment without any aliasing and using only little extra overhead by way of a multiplexer and masking circuit for diagnosis. Our solution takes into account the relatively slower speed of the tester and the reload time of the expected data to the tester memory due to limited tester memory while reducing the test/debug cost. Experimental results show that the test application time by our method can be reduced by a factor of 10 with very little hardware overhead to achieve such advantage.

Classification of Sequential Circuits Based on τk Notation and Its Applications

This paper introduces τk notation to be used to assess test generation complexity of classes of sequential circuits. Using τk notation, we reconsider and restate the time complexity of test generation for existing classes of acyclic sequential circuits. We also introduce a new DFT method called feedback shift register (FSR) scan design technique, which is extended from the scan design technique. Therefore, for a given sequential circuit, the corresponding FSR scan designed circuit has always equal or lower area overhead and test application time than the corresponding scan designed circuit. Furthermore, we identify some new classes of sequential circuits that contain some cyclic sequential circuits, which are τ-equivalent and τ2-bounded. These classes are the l-length-bounded testable circuits, l-length-bounded validity-identifiable circuits, t-time-bounded testable circuits and t-time-bounded validity-identifiable circuits. In addition, we provide two examples of circuits belonging to these classes, namely counter-cycle finite state machine realizations and state-shiftable finite state machine realizations. Instead of using a DFT method, a given sequential circuit described at the finite state machine (FSM) level can be synthesized using another test methodology called synthesis for testability (SFT) into a circuit that belongs to one of the easily testable classes of cyclic sequential circuits.

Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch

In this paper, we provide a practical formulation of the problem of identifying all error occurrences and all failed scan cells in at-speed scan based BIST environment. We propose a method that can be used to identify every error when the circuit test frequency is higher than the tester frequency. Our approach requires very little extra hardware for diagnosis and the test application time required to identify errors is a linear function of the frequency ratio between the CUT and the tester.

A Class of Linear Space Compactors for Enhanced Diagnostic

Testing of VLSI circuits is challenged by the increasing volume of test data that adds constraints on tester memory and impacts test application time substantially. Space compactors are commonly used to reduce the test volume by one or two orders of magnitude. However, such level of compaction reduces the quality of the diagnostic of faults because it is difficult to identify the locations of errors in the compacted response. In this paper, we introduce a design of space compactors that can be used in pass/fail mode as well as in diagnostic mode with enhanced performance by trading off compaction ratio for diagnostic ability. We analyze the properties of the compactors and evaluate their performance through simulations