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Dive into the research topics where Thomas Hastings Greer is active.

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Featured researches published by Thomas Hastings Greer.


international solid-state circuits conference | 2013

A 0.54 pJ/b 20 Gb/s Ground-Referenced Single-Ended Short-Reach Serial Link in 28 nm CMOS for Advanced Packaging Applications

John W. Poulton; William J. Dally; Xi Chen; John G. Eyles; Thomas Hastings Greer; Stephen G. Tell; John M. Wilson; C. Thomas Gray

Laminated packages, silicon interposer substrates, and special-purpose package-to-package interconnect [1,5], together with 3D stacking of silicon components [2] enable systems with greatly improved computational power, memory capacity and bandwidth. These package options offer very high-bandwidth channels between chips on the same substrate. We employ ground-referenced single-ended signaling, a charge-pump transmitter, and a co-designed channel to provide communication between multiple chips on one package with high bandwidth per pin and low energy per bit.


applied power electronics conference | 2016

Current parking regulator for zero droop/overshoot load transient response

Sudhir S. Kudva; William J. Dally; Thomas Hastings Greer; C. Thomas Gray

Supply voltage integrity during a load transition is a critical problem. Droop on the supply may lead to logic failures, and overshoot can reduce reliability. Voltage deviations from the nominal forces designers to apply margins in design to ensure correct operation. This paper addresses two main causes of droop/overshoot on the supply line namely the sluggish converter response and the parasitics between the converter and the load. We present current parking regulator (CPR), a voltage down-converter with almost zero droop or overshoot during a load transient along with implementation techniques to nullify the effect of the parasitics. The underlying principle involves avoiding the inductor slewing time by parking sufficient excess current in the inductor, which is available to use immediately when the need arises. The system design involves on-die, package, and PCB co-design to minimize the impact of parasitics. Measurement results show negligible droop/overshoot when the load current transitions from 0.8A to 7.5A and vice versa in 2ns with only 200nF of load capacitance on the regulated output voltage node. The design was fabricated in a 28nm CMOS technology and integrated in the same package as the load using an 8 layer substrate. It achieves a peak efficiency of 83% at 8A load current.


Archive | 2001

Phase controlled oscillator

William J. Dally; Ramin Farjad-Rad; John W. Poulton; Thomas Hastings Greer; Hiok-Tiaq Ng; Teva Stone


Archive | 2013

Ground referenced single-ended signaling

John W. Poulton; Thomas Hastings Greer; William J. Dally


Archive | 2012

Data-driven charge-pump transmitter for differential signaling

John W. Poulton; Thomas Hastings Greer; William J. Dally


Archive | 2013

On-package multiprocessor ground-referenced single-ended interconnect

William J. Dally; Brucek Khailany; John W. Poulton; Thomas Hastings Greer; Carl Thomas Gray


Archive | 2013

Ground-referenced single-ended memory interconnect

William J. Dally; John W. Poulton; Thomas Hastings Greer; Brucek Khailany; Carl Thomas Gray


Archive | 2013

Ground-referenced single-ended system-on-package

William J. Dally; John W. Poulton; Thomas Hastings Greer; Brucek Khailany; Carl Thomas Gray


Archive | 2013

GROUND-REFERENCED SINGLE-ENDED SIGNALING CONNECTED GRAPHICS PROCESSING UNIT MULTI-CHIP MODULE

William J. Dally; Jonah M. Alben; John W. Poulton; Thomas Hastings Greer


Archive | 2013

MULTI-PHASE GROUND-REFERENCED SINGLE-ENDED SIGNALING

William J. Dally; John W. Poulton; Thomas Hastings Greer

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