Robert E. Palmer
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Featured researches published by Robert E. Palmer.
international solid state circuits conference | 2007
John W. Poulton; Robert E. Palmer; Andrew M. Fuller; Trey Greer; John G. Eyles; William J. Dally; Mark Horowitz
This paper describes a 6.25-Gb/s 14-mW transceiver in 90-nm CMOS for chip-to-chip applications. The transceiver employs a number of features for reducing power consumption, including a shared LC-PLL clock multiplier, an inductor-loaded resonant clock distribution network, a low- and programmable-swing voltage-mode transmitter, software-controlled clock and data recovery (CDR) and adaptive equalization within the receiver, and a novel PLL-based phase rotator for the CDR. The design can operate with channel attenuation of -15 dB or greater at a bit-error rate of 10-15 or less, while consuming less than 2.25 mW/Gb/s per transceiver.
international solid-state circuits conference | 2007
Robert E. Palmer; John W. Poulton; William J. Dally; John G. Eyles; Andrew M. Fuller; Trey Greer; Mark Horowitz; Mark D. Kellam; F. Quan; F. Zarkeshvari
A power-efficient 6.25Gb/s transceiver in 90nm CMOS for chip-to-chip communication is presented, it dissipates 2.2mW/Gb/s operating at a BER of <10-15 over a channel with -15dB attenuation at 3.125GHz. A shared LC-PLL, resonant clock distribution, a low-swing voltage-mode transmitter, a low-power phase rotator, and a software-based CDR and an adaptive equalizer are used to reduce power
IEEE Journal of Solid-state Circuits | 2010
Brian S. Leibowitz; Robert E. Palmer; John W. Poulton; Yohan Frans; Simon Li; John Wilson; Michael Bucher; Andrew M. Fuller; John G. Eyles; Marko Aleksic; Trey Greer; Nhat Nguyen
This paper presents a 4.3 GB/s mobile memory interface that utilizes low power states with rapid transition times to support power efficient signaling over a wide range of effective bandwidths. The fastest power state transition is implemented by a global synchronous clock pause that gates dynamic power consumption without any loss of system state. Extensive use of CMOS circuit topologies, with low static power consumption, provides maximum power savings when the clocks are paused. The memory controller forwards a half bit-rate clock to the memory for synchronous communication, which is similarly paused in the low power state. Thus, dynamic interface power on the memory itself naturally responds to the clock pausing, without any explicit communication from the controller or special low-power state on the memory. Low-swing differential signaling based on a push-pull voltage mode driver results in good signal integrity and power efficiency at peak activity. Test-chips fabricated in a 40 nm low-power CMOS technology achieve 3.3 mW/Gb/s power efficiency at 4.3 GB/s data bandwidth, and support better than 5 mW/Gb/s operation over a range from 0.03 to 4.3 GB/s.
asian solid state circuits conference | 2008
Robert E. Palmer; John W. Poulton; Andrew M. Fuller; Judy Chen; Jared L. Zerbe
This paper highlights design considerations for low-power, high-performance mobile memory and logic interfaces, based on the results from the 14 mW, 6.25 Gb/s transceiver test chip demonstrated in 90 nm CMOS. One of the keys to achieving 2.25 mW/Gbps was the highly-sensitive, low-offset receiver. An accurate receiver enables low-swing signaling and requires less power and area from the transmitter. The smaller transceiver design in turn lowers the clock distribution power and improves the signal quality by presenting less loading to the clock and the channel, respectively. The improved signal quality enables even lower signal swing and a ldquospiral of goodnessrdquo continues. This paper examines these aspects in detail and discusses their potential implications to a broad spectrum of future low-power, high-performance mobile interface designs.
custom integrated circuits conference | 1992
Carry C. Heinze; Robert E. Palmer; Ian Dresser; Neil Leister
The design and performance of three full-custom CMOS circuits which form the heart of an experimental Broadband ISDN (B-ISDN) switch are discussed, The circuits are a sorter, an Omega switch, and a multi-input with priority queue controller. These chips constitute the core of a novel output buffered, self-routing, ATM switch fabric of thirtytwo ports which features multiple Ievels of cell delay and discard priority.
custom integrated circuits conference | 2011
Scott C. Best; Brian S. Leibowitz; Lei Luo; Robert E. Palmer; John Wilson; Jared L. Zerbe; Amir Amirkhany; Nhat Nguyen
Power-efficiency results from several generations of I/O interfaces with specific goals are presented as well as the tradeoffs made within and across those designs. Foundational work in active-power reduction at a single rate for a symmetric system, the subsequent application of that work to a burst-mode asymmetric interface, and recent research on low-overhead bursting are discussed. Dynamic voltage frequency scaling and efficiency increases enabled by system level interconnect improvements are also considered as important techniques.
Archive | 1999
John W. Poulton; Stephen G. Tell; Robert E. Palmer
Archive | 2009
Frederick A. Ware; Robert E. Palmer; John W. Poulton
Archive | 2004
Ramin Farjad-Rad; John W. Poulton; Thomas H. Greer; Robert E. Palmer
symposium on vlsi circuits | 2009
Robert E. Palmer; John W. Poulton; Brian S. Leibowitz; Yohan Frans; Simon Li; Andrew M. Fuller; John G. Eyles; John Wilson; Marko Aleksic; Trey Greer; Michael Bucher; Nhat Nguyen