Thomas Kreiliger

Perfect crystals grown from imperfect interfaces

The fabrication of advanced devices increasingly requires materials with different properties to be combined in the form of monolithic heterostructures. In practice this means growing epitaxial semiconductor layers on substrates often greatly differing in lattice parameters and thermal expansion coefficients. With increasing layer thickness the relaxation of misfit and thermal strains may cause dislocations, substrate bowing and even layer cracking. Minimizing these drawbacks is therefore essential for heterostructures based on thick layers to be of any use for device fabrication. Here we prove by scanning X-ray nanodiffraction that mismatched Ge crystals epitaxially grown on deeply patterned Si substrates evolve into perfect structures away from the heavily dislocated interface. We show that relaxing thermal and misfit strains result just in lattice bending and tiny crystal tilts. We may thus expect a new concept in which continuous layers are replaced by quasi-continuous crystal arrays to lead to dramatically improved physical properties.

Highly Mismatched, Dislocation-Free SiGe/Si Heterostructures

Defect-free mismatched heterostructures on Si substrates are produced by an innovative strategy. The strain relaxation is engineered to occur elastically rather than plastically by combining suitable substrate patterning and vertical crystal growth with compositional grading. Its validity is proven both experimentally and theoretically for the pivotal case of SiGe/Si(001).

Strain relaxation of GaAs/Ge crystals on patterned Si substrates

We report on the mask-less integration of GaAs crystals several microns in size on patterned Si substrates by metal organic vapor phase epitaxy. The lattice parameter mismatch is bridged by first growing 2-μm-tall intermediate Ge mesas on 8-μm-tall Si pillars by low-energy plasma enhanced chemical vapor deposition. We investigate the morphological evolution of the GaAs crystals towards full pyramids exhibiting energetically stable {111} facets with decreasing Si pillar size. The release of the strain induced by the mismatch of thermal expansion coefficients in the GaAs crystals has been studied by X-ray diffraction and photoluminescence measurements. The strain release mechanism is discussed within the framework of linear elasticity theory by Finite Element Method simulations, based on realistic geometries extracted from scanning electron microscopy images.

GaAs/Ge crystals grown on Si substrates patterned down to the micron scale

Monolithic integration of III-V compounds into high density Si integrated circuits is a key technological challenge for the next generation of optoelectronic devices. In this work, we report on the metal organic vapor phase epitaxy growth of strain-free GaAs crystals on Si substrates patterned down to the micron scale. The differences in thermal expansion coefficient and lattice parameter are adapted by a 2-μm-thick intermediate Ge layer grown by low-energy plasma enhanced chemical vapor deposition. The GaAs crystals evolve during growth towards a pyramidal shape, with lateral facets composed of {111} planes and an apex formed by {137} and (001) surfaces. The influence of the anisotropic GaAs growth kinetics on the final morphology is highlighted by means of scanning and transmission electron microscopy measurements. The effect of the Si pattern geometry, substrate orientation, and crystal aspect ratio on the GaAs structural properties was investigated by means of high resolution X-ray diffraction. The th...

Three-dimensional Ge/SiGe multiple quantum wells deposited on Si(001) and Si(111) patterned substrates

In this work we address three-dimensional heterojunctions, demonstrating that photoluminescence from defect-free, Ge/SiGe multiple quantum well (MQW) micro-crystals grown on deeply patterned Si(001) and Si(111) substrates exhibit similar radiative intensity and analogous spectral shape.

Reconstruction of crystal shapes by X‐ray nanodiffraction from three‐dimensional superlattices

Quantitative nondestructive imaging of structural properties of semiconductor layer stacks at the nanoscale is essential for tailoring the device characteristics of many low-dimensional quantum structures, such as ultrafast transistors, solid state lasers and detectors. Here it is shown that scanning nanodiffraction of synchrotron X-ray radiation can unravel the three-dimensional structure of epitaxial crystals containing a periodic superlattice underneath their faceted surface. By mapping reciprocal space in all three dimensions, the superlattice period is determined across the various crystal facets and the very high crystalline quality of the structures is demonstrated. It is shown that the presence of the superlattice allows the reconstruction of the crystal shape without the need of any structural model.

Stacking Fault Analysis of Epitaxial 3C-SiC on Si(001) Ridges

The stacking faults (SFs) in 3C-SiC epitaxially grown on ridges deeply etched into Si (001) substrates offcut towards [110] were quantitatively analyzed by electron microscopy and X-ray diffraction. A significant reduction of SF density with respect to planar material was observed for the {111} planes parallel to the ridges. The highest SF density was found in the (-1-11) plane. A previously observed defect was identified as twins by electron backscatter diffraction.

Defect Reduction in Epitaxial 3C-SiC on Si(001) and Si(111) by Deep Substrate Patterning

The heteroepitaxial growth of 3C-SiC on Si (001) and Si (111) substrates deeply patterned at a micron scale by low-pressure chemical vapor deposition is shown to lead to space-filling isolated structures resulting from a mechanism of self-limitation of lateral expansion. Stacking fault densities and wafer bowing may be drastically reduced for optimized pattern geometries.

Heterointegration of InGaAs/GaAs quantum wells on micro-patterned Si substrates

InGaAs/GaAs quantum wells (QWs) grown on μ-patterned Ge/Si substrates by metal organic vapor phase epitaxy are investigated by electron microscopy and spatially resolved photoluminescence (PL) spectroscopy. The lattice parameter mismatch of GaAs and Si is overcome by a Ge buffer layer grown by low-energy plasma enhanced chemical vapor deposition. The GaAs crystals form truncated pyramids whose shape is strongly affected by the geometry of the underlying pattern consisting of 8 μm deep and 3–50 μm wide square Si pillars. Comparing the measured PL energies with calculations performed in the effective mass approximation reveals that the QW emission energies are significantly influenced by the GaAs morphology. It is shown that the geometry favors indium diffusion during growth from the inclined facets towards the top (001) facet. The Si pillar-size dependent release of thermally induced strain observed in the PL measurements is confirmed by X-ray diffraction.

Epitaxial Ge-crystal arrays for X-ray detection

Monolithic integration of an X-ray absorber layer on a Si CMOS chip might be a potentially attractive way to improve detector performance at acceptable costs. In practice this requires, however, the epitaxial growth of highly mismatched layers on a Si-substrate, both in terms of lattice parameters and thermal expansion coefficients. The generation of extended crystal defects, wafer bowing and layer cracking have so far made it impossible to put the simple concept into practice. Here we present a way in which the difficulties of fabricating very thick, defect-free epitaxial layers may be overcome. It consists of an array of densely packed, three-dimensional Ge-crystals on a patterned Si(001) substrate. The finite gap between neighboring micron-sized crystals prevents layer cracking and substrate bowing, while extended defects are driven to the crystal sidewalls. We show that the Ge-crystals are indeed defect-free, despite the lattice misfit of 4.2%. The electrical characteristics of individual Ge/Si heterojunction diodes are obtained from in-situ measurements inside a scanning electron microscope. The fabrication of monolithically integrated detectors is shown to be compatible with Si-CMOS processing.