Thomas Ortleb

Controlling macro and micro surface topography for a 45nm copper CMP process using a high resolution profiler

Challenges in back-end-of-line process flow are becoming more critical as the 65 and 45 nm process control requirements become more stringent. Unoptimized copper CMP processing contributes to a significant portion of yield losses downstream, if electrical device performance does not address the technology node targets. Adequate metrology is required to meet the challenge of consistent wafer uniformity control in removing the excess copper on 300 mm wafers while preserving the material interface dielectrics at sub-nanometer levels. Dishing of the metal lines, which show the predictive nature of isolated in-die metal line loss, and erosion of the dielectric oxide across multiple oxide-metal line arrays are two key parameters indicative of the planarization process. As feature sizes continue to shrink, micro-dishing and edge-over-erosion become important to characterize and control. For process development, the knowledge of the macro and micro planarity will be increasingly essential to preventing lithography depth of focus issues. In manufacturing, the need for CMP process stability increases as a process excursion could occur at any time. In-line monitoring of macro and micro-level surface topography, dishing, erosion, micro-dishing, and edge-over-erosion parameter values allows fine tuning, optimization, and process control.