Thomas S. Dory

High-density compliant die-package interconnects

Reduction in inter-level dielectric (ILD) constant has been accompanied by a reduction in ILD adhesive and cohesive strength thus increasing potential for under bump (flip-chip) ILD cracking during packaging and reliability testing. Two primary mechanisms were determined to cause this failure: (1) stress on the ILD created due to the coefficient of thermal expansion (CTE) mismatch between the silicon and the package substrate; and (2) the die-to-package interconnection, i.e. the bump, transmits the CTE-induced mismatch stresses directly to the ILD (Chandran et al., 2004). Compliant die-package interconnects (Zhu et al., 2004) substituted for conventional C4 flip-chip interconnections promises to offer reduction in package induced stresses onto the silicon die consisting of low-k ILD layers. The reduction of stresses achieved with these compliant interconnects is by decoupling the die and the package substrate such that either entity is able to deform without constraining the other. Extensive thermomechanical simulation using various modeling approaches predicts an ILD stress reduction offered by compliant interconnects to be between 17-57% relative to conventional C4 flip-chip bump. A prototype compliant interconnect structure was fabricated on a low-k ILD silicon test-chip with 180mum C4 pitch and packaged onto an organic substrate with Pb-free solder. Assembly end-of-line (EOL) data was collected to assess the ILD stress reduction, warpage analysis, Imax and electromigration performance of the compliant interconnects. The focus of this paper is a comparison of the performance of compliant die-package interconnects as a substitute for conventional C4 flip-chip bump technologies in low-k ILD architectures

Ceramic Via Wafer-Level Packaging for MEMS

We will present a novel approach to wafer level packaging for micro-electro-mechanical systems. Like most common MEMS packaging methods today, our approach utilizes a wafer bonding process between a cap wafer and a MEMS device wafer. However, unlike the common methods that use a silicon or glass cap wafer, our approach uses a ceramic wafer with built-in metal-filled vias, that has the same size and shape as a standard 150 mm silicon wafer. This ceramic via wafer packaging method is much less complex than existing methods, since it provides hermetic encapsulation and electrical interconnection of the MEMS devices, as well as a solderable interface on the outside of the package for board-level interconnection. We have demonstrated successful ceramic via wafer-level packaging of MEMS switches using eutectic gold-tin solder as well as tin-silver-copper solder combined with gold thermo-compression bonding. In this paper, we will present the ceramic via MEMS package architecture and discuss the associated bonding and assembly processes.Copyright

Wafer Level Bonding of MEMS Devices Using Ceramic Lids

Wafer level bonding of MEMS devices is becoming an important packaging technique for small die. Wafer lid bonding simplifies and provides an economical assembly process. One requirement for RF MEMS devices is a hermetic lid, seal material, and sealing process for device reliability. A challenge of this packaging technique is the difference between the lid material CTE, coefficient of thermal expansion, and the silicon device wafer. We selected low temperature co-fired ceramics, LTCC, to evaluate as a potential MEMS lid material for wafer level bonding. This report covers the use of LTCC ceramic lids having CTE values of 5.5, 4.0, and 3.4ppm with thickness of 0.5 and 0.3mm. Different bonding recipes using an inert atmosphere were developed to manage warpage after bonding. Cooling ramp rates, dwell times at elevated temperatures, and lid scoring methods were investigated. A hold time at an elevated temperature was required for the ceramic lids with higher CTE values. With the low CTE ceramic lids, no hold time was required. We found successful RF MEMS wafer level bonding, WLB, can be achieved using low CTE ceramic lids.Copyright