Thomas W. Lynch

A spanning tree carry lookahead adder

The design of the 56-b significant adder used in the Advanced Micro Devices Am29050 microprocessor is described. Originally implemented in a 1- mu m design role CMOS process, it evaluates 56-b sums in well under 4 ns. The adder employs a novel method for combining carries which does not require the back propagation associated with carry lookahead, and is not limited to radix-2 trees, as is the binary lookahead carry tree of R.P. Brent and H.T. Kung (1982). The adder also utilizes a hybrid carry lookahead-carry select structure which reduces the number of carriers that need to be derived in the carry lookahead tree. This approach produces a circuit well suited for CMOS implementation because of its balanced load distribution and regular layout. >

A mechanically checked proof of the AMD5/sub K/86/sup TM/ floating-point division program

We report on the successful application of a mechanical theorem prover to the problem of verifying the division microcode program used on the AMD5/sub K/86 microprocessor. The division algorithm is an iterative shift and subtract type. It was implemented using floating point microcode instructions. As a consequence, the floating quotient digits have data dependent precision. This breaks the constraints of conventional SRT division theory. Hence, an important question was whether the algorithm still provided perfectly rounded results at 24, 53, or 64 bits. The mechanically checked proof of this assertion is the central topic of the paper. The proof was constructed in three steps. First, the divide microcode was translated into a formal intermediate language. Then, a manually created proof was transliterated into a series of formal assertions in the ACL2 dialect. After many expansions and modifications to the original proof, the theorem prover certified the assertion that the quotient will always be correctly rounded to the target precision.

The redundant cell adder

The design of the 56-b significand adder for the Advanced Micro Devices, Am29050 microprocessor, is described. This is a 1- mu m design rule CMOS realization of a high-performance RISC (reduced instruction set computer) microprocessor that implements IEEE Standard 754 floating-point arithmetic. To achieve an add time of under 4 ns for the 56-b significand and to avoid multistage pipelines which significantly impair compiler efficiency, a redundant cell adder has been developed. This redundant cell adder design combines carry lookahead adders realized with Manchester carry chains and the carry select adder concept to achieve approximately twice the speed of the traditional carry lookahead adder. This adder achieves a 3.2-ns measured add time for 56-bit operands and is of reasonable size.<<ETX>>

The K5 transcendental functions

This paper describes the development of the transcendental instructions for the K5, AMDs recently completed x86 compatible superscalar microprocessor. A multi-level development cycle, with testing between levels, facilitated the early detection of errors and limited their effect on the design schedule. The algorithms for the transcendental functions use table-driven reductions followed by polynomial approximations. Multiprecision arithmetic operations are used when necessary to maintain sufficient accuracy and to ensure that the transcendental functions have a maximum error of one unit in the last place.<<ETX>>

A High Radix On-line Arithmetic for Credible and Accurate Computing

The result of a simple floating-point computation can be in great error, even though no error is signaled, no coding mistakes are in the program, and the computer hardware is functioning correctly. This paper proposes a set of instructions appropriate for a general purpose microprocessor that can be used to improve the credibility and accuracy of numerical computations. Such instructions provide direct hardware support for monitoring events which may threaten computational integrity, implementing floating-point data types of arbitrary precision, and repeating calculations with greater precision. These useful features are obtained by the efficient implementation of high radix on-line arithmetic. The prevalence of super-scalar and VLIW processors makes this approach especially attractive.

Software for high radix on-line arithmetic

High radix on-line arithmetic provides an efficient method for performing variable-precision arithmetic. It can be implemented on conventional microprocessors using sequences of three operand instructions. This paper presents software support for high radix on-line arithmetic. This software includes emulation modules for high radix operations, and a precision analysis program for setting the input and intermediate variable tolerances necessary for guaranteed result accuracy over a specified domain.AbstractКомпьютерная арифметика оперативного доступа с большим основанием системы счисления предоставляет эффективный метод для вычислений с переменной разрядностью. Ее можно реализовать на обычных микропроцессорах с помощью последовательностей инструкций с тремя операндами. В работе представлена программная поддержка для компьютерной арифметики оперативного доступа с большим основанием системы счисления. Программное обеспечение включает в себя модули эмуляции для операций с большим основанием системы счисления, а также программу анализа разрядности, служащую для задания лопусков на исходные и промежуточные переменные, обеспечивающих гарантированную точность результата на заданной области.