Thonas Su

Delta-L methodology for efficient PCB trace loss characterization

The via effect has a big impact to the loss of the entire channel. To characterize the loss of a stripline design without the via contribution is very important for a designer to evaluate the dielectric material selection and the manufacturing process control. In this paper, an effective methodology, namely Delta-L, was proposed to remove the via effect efficiently and characterize the board electrical performance accurately.

Board-level signal integrity methodology

The board-level signal integrity, a new methodology to indicate the performance quality of a PCB channel, is introduced in this paper. Instead of the eye height and the eye width, the pseudo eye and amplitude ratio are defined as performance indicators of a PCB channel. The two applications of board-level signal integrity methodology are also given.

Channel quality comparison for OOGIO bus designs

Traditionally, Intel supports ODM/OEM (original design manufacturer / original equipment manufacturer) IO bus designs via PDG (platform design guide). If IO bus design is out of PDG guidelines (OOG), usually Intel cannot support it. However, Intel is experiencing overwhelming customer requests for OOG support since more and more customers are designing products OOG for cost vs. performance tradeoff. On the other hand, OEMs/ODMs usually have very stringent schedules and limited SI resources, and it is not practical for them to follow Intels internal complicated SI simulation process for a robust platform design. Therefore, we propose a simple but very accurate and powerful approach, channel quality comparison (CQC), to address this problem. CQC can significantly improve Intel OOG support quality and enable OEMs/ODMs to support all OOG designs. CQC also helps them to optimize PCB Design BOM cost vs. performance and reduce product development cycle for time-to-market (TTM).

Channel noise scan by using simulations of voltage regulator noise to signals

In this paper, channel noise scan approach (CNS) is proposed to efficiently analyze the potential VR-signal coupling issue in the pre-silicon design and the post-silicon debug of the platform development. CNS is based on a new simulation methodology that includes the whole PCB with signals, voltage regulator (VR) networks, and the interaction between the two. The goal of this simulation methodology is to help platform developer to quantify the VR-signal coupling risk and find the outliers of the victim signal nets according to the board layout and the VR design. This methodology can also provide the ability for the designer to do performance/cost tradeoff, layout optimization. To systematically analyze the VR-signal coupling problems, both the frequency and time domain approaches have been developed to characterize the VR-signal coupling in different levels. The frequency domain approach can quickly point out potential issues and the time domain approach is proved to be consistent with the frequency domain but with more detail and intuitive information. A design flow is given to efficiently identify the outliers of victim signals by VR noise coupling impact. Designers can improve the layout based on channel noise scan results from the simulations.

Printed circuit board insertion loss measurement metrology comparison

Channel loss is a dominant factor for the signaling performance of high-speed I/Os. Some platform design guides clearly specify the printed-circuit board (PCB) trace-only loss requirement. The via effect has a big impact on the loss of the entire channel and how to characterize the loss of a stripline design with the via effect being de-embedded is very important for a designer to select the right material and manufacturing process control, balancing the platform cost and performance requirement. An improper selection of PCB material may result in either a costly over design or an increased risk of platform performance. This is especially true for traces on a thicker board with long via or any board with long via stub. Furthermore, the impact of via and via stub is more prominent when low-loss PCB material is used. A few methods for PCB trace loss characterization have been widely used in the industry, including Thru-Reflect-Line (TRL), Delta-L and Smart Fixture De-embedding (SFD), to remove the unwanted via effect in striplines. Some of methods, such as TRL, require a series of measurement procedures with many de-embedding structures. How to effectively remove via effect through a simple, efficient, and accurate approach in the high volume measurement is critical for platform designers, as well as PCB suppliers. In this paper, a study on PCB insertion loss measurement metrology is conducted to compare the accuracy and efficiency of different characterization methods.

Improve signal integrity performance by using hybrid PCB stackup

FR4 is a commonly used material in industry to build printed circuit boards. However signals propagating in this media have significant attenuation when date rate gets higher and higher, gating the solution space. Low loss materials can be considered to enable longer board routing but they are very costly for most of commercial platforms. In this paper, hybrid PCB stackup is investigated. The investigation focuses on full channel signal integrity analysis. Simulations for SATA3 and PCIE3 show noticeable improvement of using this hybrid stackup. Such a hybrid is normally less costly than all low loss PCB stackup, thus achieving a good compromising between cost and performance for PCB design and manufacturing.

Fast signal integrity methodology for PCB pre-layout analysis and layout quality check

In this paper, a fast signal integrity methodology using pseudo eye is introduced to characterize printed circuit board (PCB) channels. The pseudo eye and pseudo ratio are proposed as performance indicators of the channel. This methodology can be applied to not only the solution space check during the pre-layout design phase but also layout quality check before PCB manufacture. For pre-layout analysis, the fast methodology can significantly reduce the required simulation resource and remove the complexity of chip behaviors with the equalization (EQ) function. Moreover, the PCB layout can be very efficiently checked and the potential routing issues can be quickly identified.

A linear 4-element model of VRM —Characteristics, practical uses and limitations

This paper discusses the characteristics and limitations of a 4-element linear model of a voltage regulator module (VRM) by comparing it with a state average model (SAM) with feedback used by Intel. A virtual load line method is proposed to correlate the 4-element linear model by introducing a modified DC resistance. The resultant impedance profile is in good agreement up to 2GHz with that by original SAM. Furthermore, it can be simplified to a 2-element model, which still gives good agreement since the high frequency impedance is dominated by the bulk capacitance in realistic PDNs.

Cost-effective characterization of dissipative loss of printed circuit board traces

Determining how to accurately estimate and control the loss of a channel is critical to the success of the design of a high-speed I/O link. As Printed circuit boards (PCB) continue to be a key ingredient of a computer system design, the cost-effective characterization of the PCB materials and the measurement of the loss PCB traces in a given stackup have become a necessary step in the computer design cycle. In this paper, the measurement methods for the PCB trace loss are discussed and compared. A cost-effective method, namely Delta-L, is introduced and analyzed in detail. The method has been widely applied in the loss characterization of PCB traces in the server computer system designs. The simulation and measurement results are presented to show the effectiveness and accuracy of the method.

Electrical characterization for performance-driven printed circuit board

During the initial design stage, PCB material selection, platform designers would like to have the accurate loss measurement to meet the channel requirement, because the PCB material contributes largely to the platform cost. In this paper, we analyze how transmission line design affects insertion loss quantity at high operation frequency. The insertion loss at 12.89GHz is measured, and it is convenient to directly correspond to channel loss simulation for 25G applications. Moreover, eight material types are validated and compared by systematic measurement. We utilize delta-L methodology to measure PCB material electrical characteristics, and show a possible way to enable PCB ecosystem having a standardization measurement procedure.