Jimmy Hsu

Delta-L methodology for efficient PCB trace loss characterization

The via effect has a big impact to the loss of the entire channel. To characterize the loss of a stripline design without the via contribution is very important for a designer to evaluate the dielectric material selection and the manufacturing process control. In this paper, an effective methodology, namely Delta-L, was proposed to remove the via effect efficiently and characterize the board electrical performance accurately.

Inter-layer crosstalk management in differential dual-striplines

Dual-stripline is gaining popularity in computer designs to save printed circuit board (PCB) cost and achieve more compact form factor. A key concern in dual-stripline design is the inter-layer crosstalk (ILC). In this paper, differential dual-stripline crosstalk is investigated, and a complete design strategy is provided. In addition to the conventional crosstalk mitigation techniques, an innovative wiring technique is proposed to reduce ILC for parallel dual-striplines. The proposed routing strategy can effectively mitigate the impact of ILC, and, as a result, enable high-density PCB layout, achieve compact form factor, and save the bill of material (BOM) cost.

Board-level signal integrity methodology

The board-level signal integrity, a new methodology to indicate the performance quality of a PCB channel, is introduced in this paper. Instead of the eye height and the eye width, the pseudo eye and amplitude ratio are defined as performance indicators of a PCB channel. The two applications of board-level signal integrity methodology are also given.

Channel noise scan by using simulations of voltage regulator noise to signals

In this paper, channel noise scan approach (CNS) is proposed to efficiently analyze the potential VR-signal coupling issue in the pre-silicon design and the post-silicon debug of the platform development. CNS is based on a new simulation methodology that includes the whole PCB with signals, voltage regulator (VR) networks, and the interaction between the two. The goal of this simulation methodology is to help platform developer to quantify the VR-signal coupling risk and find the outliers of the victim signal nets according to the board layout and the VR design. This methodology can also provide the ability for the designer to do performance/cost tradeoff, layout optimization. To systematically analyze the VR-signal coupling problems, both the frequency and time domain approaches have been developed to characterize the VR-signal coupling in different levels. The frequency domain approach can quickly point out potential issues and the time domain approach is proved to be consistent with the frequency domain but with more detail and intuitive information. A design flow is given to efficiently identify the outliers of victim signals by VR noise coupling impact. Designers can improve the layout based on channel noise scan results from the simulations.

Printed circuit board insertion loss measurement metrology comparison

Channel loss is a dominant factor for the signaling performance of high-speed I/Os. Some platform design guides clearly specify the printed-circuit board (PCB) trace-only loss requirement. The via effect has a big impact on the loss of the entire channel and how to characterize the loss of a stripline design with the via effect being de-embedded is very important for a designer to select the right material and manufacturing process control, balancing the platform cost and performance requirement. An improper selection of PCB material may result in either a costly over design or an increased risk of platform performance. This is especially true for traces on a thicker board with long via or any board with long via stub. Furthermore, the impact of via and via stub is more prominent when low-loss PCB material is used. A few methods for PCB trace loss characterization have been widely used in the industry, including Thru-Reflect-Line (TRL), Delta-L and Smart Fixture De-embedding (SFD), to remove the unwanted via effect in striplines. Some of methods, such as TRL, require a series of measurement procedures with many de-embedding structures. How to effectively remove via effect through a simple, efficient, and accurate approach in the high volume measurement is critical for platform designers, as well as PCB suppliers. In this paper, a study on PCB insertion loss measurement metrology is conducted to compare the accuracy and efficiency of different characterization methods.

Improve signal integrity performance by using hybrid PCB stackup

FR4 is a commonly used material in industry to build printed circuit boards. However signals propagating in this media have significant attenuation when date rate gets higher and higher, gating the solution space. Low loss materials can be considered to enable longer board routing but they are very costly for most of commercial platforms. In this paper, hybrid PCB stackup is investigated. The investigation focuses on full channel signal integrity analysis. Simulations for SATA3 and PCIE3 show noticeable improvement of using this hybrid stackup. Such a hybrid is normally less costly than all low loss PCB stackup, thus achieving a good compromising between cost and performance for PCB design and manufacturing.

Fast signal integrity methodology for PCB pre-layout analysis and layout quality check

In this paper, a fast signal integrity methodology using pseudo eye is introduced to characterize printed circuit board (PCB) channels. The pseudo eye and pseudo ratio are proposed as performance indicators of the channel. This methodology can be applied to not only the solution space check during the pre-layout design phase but also layout quality check before PCB manufacture. For pre-layout analysis, the fast methodology can significantly reduce the required simulation resource and remove the complexity of chip behaviors with the equalization (EQ) function. Moreover, the PCB layout can be very efficiently checked and the potential routing issues can be quickly identified.

Dual-striplines design optimizations for minimum crosstalk

Dual-stripline is widely used in the computer systems to save printed circuit board (PCB) cost and achieve more compact form factor. Many design parameters can affect the overall performance of the dual-striplines. In this paper, the optimization of the dual-stripline design is discussed in detail, such as stackup selection, component breakout, etc. Theory analysis as well as Three-Dimensional full-wave modelling results of the inter-layer crosstalk for both single-ended and differential dual-stripline are presented to understand the inter-layer crosstalk. Measurement data from a test board is used to correlate the modeling result. An end-to-end simulation flow is proposed to precisely evaluate the overall crosstalk and full-link performance of a design with dual-stripline.

Broad-side crosstalk mitigation in dual-stripline designs

Dual-striplines are gaining popularity in the high-density computer system designs to save printed circuit board (PCB) cost and achieve smaller form factor. However, broad-side near-end/far-end crosstalk (NEXT/FEXT) between dualstriplines is a major concern that potentially has a significant impact to the signal integrity. In this paper, the broadside coupling between two differential pairs, and a differential pair and a single-ended trace in a dual-stripline design, is investigated and characterized. An innovative design methodology and routing strategy are proposed to effectively mitigate the broad-side coupling without additional routing space.

Cost-effective characterization of dissipative loss of printed circuit board traces

Determining how to accurately estimate and control the loss of a channel is critical to the success of the design of a high-speed I/O link. As Printed circuit boards (PCB) continue to be a key ingredient of a computer system design, the cost-effective characterization of the PCB materials and the measurement of the loss PCB traces in a given stackup have become a necessary step in the computer design cycle. In this paper, the measurement methods for the PCB trace loss are discussed and compared. A cost-effective method, namely Delta-L, is introduced and analyzed in detail. The method has been widely applied in the loss characterization of PCB traces in the server computer system designs. The simulation and measurement results are presented to show the effectiveness and accuracy of the method.