Tiago Reimann

Effective Method for Simultaneous Gate Sizing and

This paper presents a fast and effective approach to gate-version selection and threshold voltage, Vth, assignment. In the proposed flow, first, a solution without slew and load violation is generated. Then, a Lagrangian Relaxation (LR) method is used to reduce leakage power and achieve timing closure while keeping the circuit no or few violations. If the set of gate-versions given by LR produces a circuit with negative slack, a timing recovery method is applied to find near zero positive slack. The solution without negative slack is finally introduced to a power reduction step. For the ISPD 2012 Contest benchmarks, the leakage power of our solutions is, on average, 9.53% smaller than and 12.45% smaller than . The sizing produced using our approach achieved the first place in the ISPD 2013 Discrete Gate Sizing Contest with, on average, 8.78% better power results than the second place tool. With new timing calculation applied, this flow can provide, on average, an extra 9.62% power reduction compared to the best Contest results. This flow is also the first gate sizing method to report violation-free solutions for all benchmarks of the ISPD 2013 Contest.

V

This paper presents a flow composed by a set of heuristic algorithms to address the discrete gate sizing and Vt assignment problem for leakage power minimization while satisfying delay, load and slew constraints. The proposed flow combines the Fanout-of-4 empirical rule, the Logical Effort concept, a Simulated Annealing (SA) as the main engine, as well as a new set of specific optimization strategies to solve this difficult problem as formulated in the 2012 ISPD Gate Sizing Contest. The main contribution of this work is to show how a sequence of Simulated Annealing runs, starting from a solution given by Logical Effort, Fanout of-4 rule, and employing a set of new techniques can be used together to solve gate sizing problems of up to a million gates. New methods are presented to solve violations during the Annealing and a dynamic cost function is presented that helps SA to achieve different conflicting tasks during the optimization. The entire flow was able to achieve the second and first ranks in the ISPD 2012 Contest. A set of different experiments is presented to support design decisions and highlight the quality of the achieved results.

th Assignment Using Lagrangian Relaxation

Timing-constrained power-driven gate sizing has aroused lot of research interest after the recent two discrete gate sizing contests organized by International Symposium on Physical Design. Since then, there are plenty of research papers published and new algorithms are proposed based on the ISPD 2013 contest formulation. However, almost all (new and old) papers in the literature ignore the details of how power-driven gate sizing fits in industrial physical synthesis flows, which limits their practical usage. This paper aims at filling this knowledge gap. We explain our approach to integrate a state-of-the-art Lagrangian Relaxation-based gate sizing into our actual physical synthesis framework, and explain the challenges and issues we observed from the point of view of VLSI design flows.

Simultaneous gate sizing and Vt assignment using Fanin/Fanout ratio and Simulated Annealing

This paper presents a fast and effective approach to cell-type selection and Vth assignment. In our approach, initially a solution without slew and load violation is generated. Then, the Lagrangian Relaxation considering lambda-delay sensitivities is used to reduce leakage power trying to keep the circuit without timing and load violations. If the set of cell-types given by Lagrangian Relaxation produces a circuit with negative slack, a timing recovery method is applied to find near-zero positive slack. The solution without negative slack is introduced to a power reduction step. The sizing produced using our approach could achieve up to 28% in power reduction compared to state of the art works. The leakage power of our solutions is, on average, 9.53% smaller than [1] and 12.45% smaller than [2]. Furthermore, the method is 19× faster than [1] and 1.18× faster than [2].

Gate sizing and threshold voltage assignment for high performance microprocessor designs

In recent years, an increasing number of papers have focused on the cell selection problem. However, previous papers fail to consider the actual problems of performing cell selection in the after placement and CTS optimization stages of industrial designs. This paper discusses the obstacles found when applying state-of-the-art Lagrangian relaxation-based cell selection in a real industrial flow. Solutions to such obstacles are presented, filling the gap in previous literature. We propose a new method to find a suitable set of initial Lagrange multipliers based on the initial gates sizes in the netlist. Fast convergence in the presence of small timing violations is achieved by a novel Lagrange multiplier update method. Our new timing-constrained formulation incorporates and balances both power and area as optimization objectives. We also present a ranking method to reduce sign-off timer calls that gives a 10x speed up in the cell selection process. Experimental results show quality improvements on a set of already deeply timing, power and area-optimized high-performance industrial microprocessor blocks with very tight constraints. Leakage power reduction of up to 18.2% is achieved (10.8% total and 7.2% on average), while timing, area and dynamic power are also improved.

Simultaneous gate sizing and V th assignment using Lagrangian Relaxation and delay sensitivities

Despite the existence of several other alternatives for estimating delay of interconnects, the Elmore Delay Model still has been used for comparison of routing algorithms. The criterion used to establish Elmores model as a confident metric for this purpose is the so-called Fidelity Property. In this work we investigate the Fidelity Property using nowadays interconnect parameters, in four routing scopes. For the first time the Fidelity is evaluated in actual algorithms comparison, one of the main utilities it was established for. What is found is that the original methodology used to evaluate this property hides a significant standard deviation. This standard deviation strongly impacts the capacity of Elmores model to provide good certainty of choosing the best routing solutions among several ones. Additionally, the experiments of algorithms comparison show that different routing alternatives are appropriated for different routing scopes, with respect to metal layers, driver strengths and routing areas.

Cell Selection for High-Performance Designs in an Industrial Design Flow

We evaluate Elmore-based Interconnect Delay Models under nanoscale technology parameters. Due to a large delay overestimation Elmore delay provides at specific nodes, some attempts to provide more accurate models have been made. However, without reasonable parameters corresponding to actual cmos processes generations, the evaluation of the derived models is potentially dubitable. With technology parameters corresponding to the smaller feature sizes available, we evaluate the ac-curacy of Elmore-based delay models in nowadays VLSI scenarios. Besides an overview of the delay models behavior along technological scaling, we measure the different accuracy for intermediate/local and long/global interconnects.

The Fidelity Property of the Elmore Delay Model in actual comparison of routing algorithms

Timing-constrained power-driven gate sizing has aroused lot of research interest after the recent discrete gate sizing contests organized by International Symposium on Physical Design. Since then, there are plenty of research papers published and new algorithms are proposed based on the contest formulation. However, almost all (new and old) papers in the literature ignore the details of how power-driven gate sizing fits in industrial physical synthesis flows, which limits their practical usage. This paper aims at filling this knowledge gap. We explain our approach to integrate a state-of-the-art Lagrangian Relaxation-based gate sizing into our actual physical synthesis framework, and explain the challenges and issues we observed from the point of view of VLSI design flows. HighlightsState-of-the-art cell selection algorithm applied in an industrial design flow.The challenges found, some solutions and preliminary results.Experiments using high-performance microprocessor blocks with modern cell library.Discuss challenges and requirements yet to be solved to further stimulate research.Results show how usual formulations fail when directly applied to industrial flows.Also show that current industrial algorithms do not provide near-optimal solutions.

On the accuracy of Elmore-based Delay Models

This work presents methods to identify and treat circuit areas that have high overflow and interconnect demand, during global routing step. In that way, two cost pre-allocation techniques are presented: the first is applied during the pre-routing congestion estimation step of the global routing flow; the second technique will act during the iterative routing phase, where the the congestion is updated on each routing round and the congestion hot spots can be identified. Since the congestion hot spots are identified, a cost calibration step is executed using the proposed congestion look-ahead techniques. The focus of these algorithms is to speed up the convergence of the global routing solution while trying to reduce the side effects in wire length. Our experiments shows a speed up of up to 1.357x with 1.39% of maximum increase in wirelength when compared to the reference implementation for the ISPD 2008 benchmarks.

Challenges of cell selection algorithms in industrial high performance microprocessor designs

Whenever new routing algorithms are proposed, corresponding performance gains are reported. Are these gains the same for different interconnect scenarios? Do the proposed techniques always outperform the previous ones in all possible routing scopes? We found out that the answer for these questions is no. In this work we evaluate several routing algorithms under an extensive set of experiments and different interconnect scenarios. The results show that different algorithms are preferable according to the different routing scopes, process generations and net sizes.