Gracieli Posser

Effective Method for Simultaneous Gate Sizing and

This paper presents a fast and effective approach to gate-version selection and threshold voltage, Vth, assignment. In the proposed flow, first, a solution without slew and load violation is generated. Then, a Lagrangian Relaxation (LR) method is used to reduce leakage power and achieve timing closure while keeping the circuit no or few violations. If the set of gate-versions given by LR produces a circuit with negative slack, a timing recovery method is applied to find near zero positive slack. The solution without negative slack is finally introduced to a power reduction step. For the ISPD 2012 Contest benchmarks, the leakage power of our solutions is, on average, 9.53% smaller than and 12.45% smaller than . The sizing produced using our approach achieved the first place in the ISPD 2013 Discrete Gate Sizing Contest with, on average, 8.78% better power results than the second place tool. With new timing calculation applied, this flow can provide, on average, an extra 9.62% power reduction compared to the best Contest results. This flow is also the first gate sizing method to report violation-free solutions for all benchmarks of the ISPD 2013 Contest.

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Electromigration (EM) in on-chip metal interconnects is a critical reliability failure mechanism in nanometer-scale technologies. This work addresses the problem of EM on signal interconnects within a standard cell. An approach for modeling and efficient characterization of cell-internal EM is developed, incorporating Joule heating effects, and is used to analyze the lifetime of large benchmark circuits. Further, a method for optimizing the circuit lifetime using minor layout modifications is proposed.

th Assignment Using Lagrangian Relaxation

This paper presents a flow composed by a set of heuristic algorithms to address the discrete gate sizing and Vt assignment problem for leakage power minimization while satisfying delay, load and slew constraints. The proposed flow combines the Fanout-of-4 empirical rule, the Logical Effort concept, a Simulated Annealing (SA) as the main engine, as well as a new set of specific optimization strategies to solve this difficult problem as formulated in the 2012 ISPD Gate Sizing Contest. The main contribution of this work is to show how a sequence of Simulated Annealing runs, starting from a solution given by Logical Effort, Fanout of-4 rule, and employing a set of new techniques can be used together to solve gate sizing problems of up to a million gates. New methods are presented to solve violations during the Annealing and a dynamic cost function is presented that helps SA to achieve different conflicting tasks during the optimization. The entire flow was able to achieve the second and first ranks in the ISPD 2012 Contest. A set of different experiments is presented to support design decisions and highlight the quality of the achieved results.

A systematic approach for analyzing and optimizing cell-internal signal electromigration

Breaking-through algorithms have been proposed in the latest years enabling the new paradigm of library-free automatic layout synthesis. Library-free synthesis is known to achieve a huge reduction in the number of transistors required to implement a circuit, reducing leakage power consumption. On the other hand, automatic-generated cells are expected to have a larger area than designed-by-hand ones. In this paper we evaluate the layout quality of an automatic generated cell library by ASTRAN, showing that even reducing the set of cells to the ones available in a commercial cell library, the cells generated by our tool gives a better result than the library ones. Our experiments suggests that, although the automatic generated cells layout is less dense, therefore having larger cell areas, timing and power are similar and input capacitances are smaller. Those characteristics result in a design with a speed increased by 12% in average and with a 24% in average smaller power consumption in our test cases.

Simultaneous gate sizing and Vt assignment using Fanin/Fanout ratio and Simulated Annealing

Electromigration (EM) in on-chip metal interconnects is a critical reliability-driven failure mechanism in nanometer-scale technologies. This paper addresses the problem of EM on signal interconnects and on Vdd and Vss rails within a standard cell. An approach for modeling and efficient characterization of cell-internal EM is developed, incorporating Joule heating effects. We also present a graph-based algorithm that computes the currents when the pin position is moved avoiding a new characterization for each pin position and consequently considerably reducing the characterization time. We use the cell lifetime analysis to determine the lifetime of large benchmark circuits, and show that these circuit lifetimes can be improved by about 2.5×-161× by avoiding the EM-critical output, Vdd, and Vss pin positions of the cells, using minor layout modifications.

A study on layout quality of automatic generated cells

Electromigration (EM) is a significant problem in integrated circuits and can seriously damage interconnect wires and vias, reducing the circuits lifetime. In this paper we are simulating the EM effects on 6 different metal layers for different wire lengths incorporating Joule heating effects. The layouts are constructed considering the 45nm technology and scaled to 22nm technology. We are simulating the EM effects considering three different wire lengths, 100μm, 200μm and 300μm in 22nm technology for a reference frequency of 2GHz. The delay is also analyzed and it increases when the wire length increases and decreases for a higher metal layer.

Cell-Internal Electromigration: Analysis and Pin Placement Based Optimization

This paper presents a fast and effective approach to cell-type selection and Vth assignment. In our approach, initially a solution without slew and load violation is generated. Then, the Lagrangian Relaxation considering lambda-delay sensitivities is used to reduce leakage power trying to keep the circuit without timing and load violations. If the set of cell-types given by Lagrangian Relaxation produces a circuit with negative slack, a timing recovery method is applied to find near-zero positive slack. The solution without negative slack is introduced to a power reduction step. The sizing produced using our approach could achieve up to 28% in power reduction compared to state of the art works. The leakage power of our solutions is, on average, 9.53% smaller than [1] and 12.45% smaller than [2]. Furthermore, the method is 19× faster than [1] and 1.18× faster than [2].

Analyzing the electromigration effects on different metal layers and different wire lengths

In modern integrated circuits, the Electromigration (EM) effects are not just seen on power delivery networks. EM is also an increasing problem in the internal metal wires of cells, referred as cell-internal signal Electromigration. In this work we present a detailed analysis of the cell-internal signal Electromigration effects considering different logic gates. The lifetime optimization by placing the output pin of the gates is dependent of the output wire shape and the logic of the gate. We are also presenting ways to improve the lifetime of the cells optimizing the cell layout.

Simultaneous gate sizing and V th assignment using Lagrangian Relaxation and delay sensitivities

This paper investigates the impact of the main sources of variation on performance and power consumption for different transistor sizing techniques applied to cells in FinFET technologies. The analysis considers process, voltage and temperature variations, individually. Voltage and temperature variations are combined to obtain an insight into their contributions. Results are useful to define the variability contributions in the early design steps and to select the most appropriate transistor sizing technique for a targeted application. Results provide a quantitative understanding of each contribution considering a 14nm FinFET technology.

Reducing the signal Electromigration effects on different logic gates by cell layout optimization

Electromigration (EM) effects are a high concern in power delivery networks where the current flow is unidirectional. As the integrated circuits (IC) technology nodes become smaller, the EM effects become a critical reliability failure mechanism also on signal nets. Such effect is also known as AC electromigration. This work presents a design strategy using special signal non-default routing rules (SSNDRs) to re-route the wire segments of critical nets that present a high current density and are EM-unsafe. Some EM-aware design steps are added in the traditional design flow to analyze, fix and improve the Mean Time to Failure (MTTF) of the designs.