Tian Dayu

Thermal experiment of silicon PIN detector

The experiment of this paper is the thermal test of the leakage current of silicon PIN detector. Raising temperature may cause the detector to increase leakage current, decrease depletion and increase noise. Three samples are used in the experiment. One (called ΔE) is the sample of 100 μm in thickness. The other two (called E1 and E2) are stacks of five detectors of 1000 μm in thickness. All of them are 12 mm in diameter. The experiment has been done for 21 hours and with power on continuously. The samples have undergone more than 60°C for about one hour. They are not degenerated when back to the room temperature. The depletion rate is temperature and bias voltage related. With the circuit of the experiment and temperature at 35°C, ΔE is still depleted while E1 and E2 are 94.9% and 99.7% depleted respectively. The noises of the samples can be derived from the values at room temperature and the thermal dependence of the leakage currents. With the addition of the noise of the pre-amplifier, the noises of E1, E2 and ΔE at 24°C are 16.4, 16.3, and 10.5 keV (FWHM) respectively while at 35°C are about 33.6, 33.1, and 20.6 keV (FWHM) respectively.

The effect of calcination temperature on nanosized tin oxide thin film

The effect of calcination on nanosized tin oxide film prepared by direct current reactive magnetron sputtering is investigated. The tin oxide semiconductors were calcined at different temperatures ranging from 400/spl deg/C to 900/spl deg/C. The testing results from SEM, XRD, XPS and the HP4145B semiconductor analyzer show that the composition, crystallinity and the resistance of the thin films change with the variation of calcination temperature.

A new release process in surface micromachining-double mask technology

This paper presents a new process for releasing micromechanical structures in surface micromachining with polysilicon support and LPCVD Si/sub 3/N/sub 4/ embedded mask for one polysilicon layer process, which is CMOS compatible and can be adjusted to be suitable for the structure stiffness by changing the distance between two supports. This process may be used for multipolysilicon layer process. The results of test structures show that this process may be a good technology to eliminate the sticking of microstructures to the substrate during the wafer drying after the sacrificial etching process.