Tianxiong Xue

Performance-Driven Steiner Tree Algorithms for Global Routing

This paper presents two performance-driven Steiner tree algorithms for global routing which consider the minimization of timing delay during the tree construction as the goal. One algorithm is based on nonlinear optimization method, another uses heuristic approach to guide the construction of Steiner tree. A new timing model is established which includes both total length and critical path between source and sink in delay formulation, and an upper bound for timing delay is deducted and used to guide both algorithms. Experiment results are given to demonstrate the effectiveness of the two algorithms.

A sensitivity-based wiresizing approach to interconnect optimization of lossy transmission line topologies

This paper presents a sensitivity-based wiresizing algorithm for interconnect delay optimization of lossy transmission line topology under MCM technologies. Our approach computes the maximum delay and its sensitivities with respect to the widths of wires in the topology via high order moments based on an exact moment matching model. Compared with other approaches, it achieves analytical sensitivity computation and calculates higher order moments (sensitivities) recursively from lower order moments for tree network. It can yield optimal wiresizing solution for interconnect delay minimization. Experiments show that the delay estimation using high order moments is very accurate compared with SPICE simulation and our approach can reduce the maximum rising delay by over 60% with small penalty in routing area. Besides delay optimization, the final solution eliminates the over-shoot of response waveform and is robust under parameter variations.

TIGER: an efficient timing-driven global router for gate array and standard cell layout design

In this paper, we propose an efficient timing-driven global router, TIGER, for gate array and standard cell layout design. Unlike other conventional global routing techniques, interconnection delays are modeled and included during the routing and rerouting process in order to minimize the maximum channel density for gate arrays or the total track number for standard cells, as well as to satisfy the timing constraints in TIGER. The timing-driven global routing problem is formulated as a multiterminal, multicommodity network flow problem with integer flows under additional timing constraints. Two novel performance-driven Steiner tree algorithms are proposed to generate the initial global routing trees. A critical-path-based timing analysis method is used to guarantee the satisfaction of timing constraints. Experimental results based on MCNC (ISCAS) benchmarks show that TIGER can obtain better results than or comparable results with TimberWolf 5.6.

Post routing performance optimization via multi-link insertion and non-uniform wiresizing

Most existing performance-driven and clock routing algorithms construct optimal routing topology for each net individually without considering its routability on the chip, so they can not guarantee performance after all nets are routed. This paper proposes a new approach for post routing performance optimization via multi-link insertion and non-uniform wiresizing, which improves the performance of a net topology obtained from a global routing solution. Unlike previous approaches, it can achieve reduction in both maximum delay and skew to satisfy user specified constraints and minimizes the routing resource consumed. During optimization, the topology of the net is kept routable. Experiments show that link insertion and wiresizing can improve net performance significantly, and among all approaches, multi-link insertion and wiresizing achieves the best performance and area efficiency.

New approaches for on-chip power switching noise reduction

The effect of power supply switching noise is gaining importance with increasing switching speeds and density of VLSI chips. Yet, todays design methodology does not adequately address this problem at chip level. This paper proposes two approaches for on-chip power switching noise reduction. The first approach aims at reducing Delta-I noise by inserting decoupling capacitors in an optimized manner. The second approach reduces the switching noise by wire-sizing power bus segments near each power pin. Both approaches are assessed by simulation of a circuit, in which power supply rails are modeled as lossy transmission lines. The results of the simulated example demonstrate the effectiveness of our approaches.

Post routing performance optimization via tapered link insertion and wiresizing

Most existing performance-driven and clock routing algorithms can not guarantee performance after all nets are routed. This paper proposes a new post routing approach which can reduce both maximum delay and skew of an existing routing topology by tapered little insertion and non-uniform wiresizing. It uses the Sequential Quadratic Programming method for constrained optimization. Experimental results show that our approach can improve performance significantly and consume less area than uniform wiresizing.

Moment models of general transmission lines with application to interconnect analysis and optimization

In this paper, we present new moment models for uniform, nonuniform and coupled transmission lines. The moment model of a line is based on the relationships between the two port currents (KCL) and the two port voltages (KVL) of the line. The parameters of the model depend on the mean values of the voltage moments and the weighted voltage moments of the line. Simple formulas are given to compute these mean values efficiently. By using such models and moment matching techniques, interconnects modeled as transmission line networks can be efficiently simulated. In addition, by using moment sensitivities, we demonstrate that wire sizing optimization can be carried out for layout design.