Tim Piessens

Nanosecond Delay Floating High Voltage Level Shifters in a 0.35

We present novel circuits for high-voltage digital level shifting with zero static power consumption. The conventional topology is analysed, showing the strong dependence of speed and dynamic power on circuit area. Novel techniques are shown to circumvent this and speed up the operation of the conventional level-shifter architecture by a factor of 5-10 typically and 30-190 in the worst case. In addition, these circuits use 50% less silicon area and exhibit a factor of 20-80 lower dynamic power consumption typically. Design guidelines and equations are given to make the design robust over process corners, ensuring good production yield. The circuits were fabricated in a 0.35 high-voltage CMOS process and verified. Due to power and IO speed limitation on the test chip, a special ring oscillator and divider structure was used to measure inherent circuit speed.

\mu

The design of a high-voltage output driver in a digital 0.25-/spl mu/m 2.5-V technology is presented. The use of stacked devices with a self-biased cascode topology allows the driver to operate at three times the nominal supply voltage. Oxide stress and hot carrier degradation is minimized since the driver operates within the voltage limits imposed by the design rules of a mainstream CMOS technology. The proposed high-voltage architecture uses a switching output stage. The realized prototype delivers an output swing of 6.46 V to a 50-/spl Omega/ load with a 7.5-V supply and an input square wave of 10 MHz. A PWM signal with a dual-tone sinusoid at 70 kHz and 250 kHz results in an IM3 of -65 dB and an IM2 of -67 dB. The on-resistance is 5.9 /spl Omega/.

m HV-CMOS Technology

Self-oscillating power amplifiers (SOPAs) provide an elegant way to power signals which have high crest factors with a high efficiency. Recently, it has been shown that by pushing this concept to its limits, the stringent specifications of digital subscriber line (xDSL) could be met. For the design of these high bandwidth, low distortion amplifiers in a digital CMOS technology, a thorough analysis of the hard nonlinear system is mandatory. This paper describes behavioral models based on the describing function method and Bessel series expansion of nonlinear modulations. Models have been derived for the self-oscillation, the bandwidth, the dominant third-order distortion and all inter-modulation products of a SOPA line driver. All spectral peaks at the output of a single ended SOPA amplifier are qualitatively and quantitatively explained by these models with a very high accuracy. A calculation speed-up with three orders of magnitude could be obtained compared with a dedicated numerical simulator.

A high-voltage output driver in a 2.5-V 0.25-/spl mu/m CMOS technology

Recently, with development of xDSL technologies, design of line drivers regains attention since the thermal limitation at the central office side (CO) demands high-efficiency line drivers. This specification becomes more severe since for the ADSL standard Discrete Multi Tone (DMT) modulation is chosen. DMT signals have a high crest factor (CF=V/sub max//V/sub min/) and demand a highly-linear line driver. Since efficiency of a class AB line driver ideally is inverse proportional to the CF, the efficiency of this type of line driver is low in DMT-based applications. When implementing a line driver in a mainstream CMOS technology, decreasing supply voltage increases this problem, since a higher quiescent current is necessary to maintain the same distortion levels. This paper depicts the principle of the differential self-oscillating power amplifier (SOPA).

Behavioral analysis of self-oscillating class D line drivers

The design of two highly efficient line drivers in a digital 0.35-/spl mu/m, 3.3-V technology are presented. The self-oscillating power amplifier (SOPA) architecture has been developed in order to obtain a high efficiency for systems with a high crest factor like discrete multitone modulated xDSL modems. The SOPA architecture is an unclocked switching-type line driver. By using self-oscillation and noise-shaping, a high signal linearity can be obtained for low over-switching ratios. By coupling two SOPA line drivers with a signal transformer, the two limit cycle oscillations are pulled toward synchronization. This gives an important mean switching frequency suppression toward the line. The need for an extra filter dealing with the mean switching frequency is in that way heavily relaxed. A zeroth-order SOPA and a third-order SOPA are prototyped. The zeroth-order line driver meets ADSL-Lite specifications with a missing tone power ratio (MTPR) of 41 dB for an 800-kHz bandwidth. The maximum efficiency is 41%. The third-order version meets ADSL and VDSL specifications with an MTPR of 56 dB and an 8.6-MHz bandwidth. An efficiency of 47% was measured for an ADSL signal with a crest factor >5.

SOPA: A high-efficiency line driver in 0.35 /spl mu/m CMOS using a self-oscillating power amplifier

In this paper, a complete high-voltage concept is presented, designed in a low- voltage CMOS technology, using only the nominal voltage as input. A test chip has been developed with an inductive DC-DC converter generating a 10V output from a single 3.3V input in a standard 1.8V/3.3V 0.18μm CMOS technology. The generated 10V serves as a supply for an on-chip Class-D output stage, able to deliver 1.5W. The 10V is protected by a custom high-voltage ESD clamp. Reliable operation of the low-voltage devices is guaranteed, including process, power supply and temperature variations, without the need for special startup circuits.

Highly efficient xDSL line drivers in 0.35-/spl mu/m CMOS using a self-oscillating power amplifier

A robust 7.5 V output driver is realized in standard 2.5 V 0.25 /spl mu/m CMOS. The chip delivers an output swing of 6.46 V to a 50 /spl Omega/ load with a 10 MHz input square wave. A dual-tone PWM signal at 70 kHz and 250 kHz results in an IM3 of -65 dBm. The on-resistance is 5.9 /spl Omega/.

A 1.5W 10V-output Class-D amplifier using a boosted supply from a single 3.3V input in standard 1.8V/3.3V 0.18μm CMOS

We report an active, medical-grade, high resolution, high dynamic range X-ray backplane based on a-IGZO thin-film technology with fast readout. This enables low dose, video rate X-ray imaging. Fast X-ray imaging will find its applications not only in medical, but also in non-destructive inspection. Curved imagers will yield sharper images when illuminated from a point source. This has been achieved thanks to superior a-IGZO technology and a pixel topology that improves noise performance and allows a cost-effective external readout.

A high-voltage output driver in a standard 2.5 V 0.25 /spl mu/m CMOS technology

Oscillator pulling towards synchronisation is one of the most important parasitic effects of a self-oscillating non-linear system. Although mostly unwanted, it can be used in self-oscillating power amplifiers (SOPA) as an inherent filtering function of the mean switching frequency. This paper describes a mathematical model to calculate the dominant oscillation mode in coupled self-oscillating power amplifiers and quantifies the major design criteria for the wanted oscillation mode. The obtained results were verified by a prototyped SOPA in a 0.35 /spl mu/ CMOS technology. The first inter-modulation band was completely suppressed, relaxing the filter requirements with 20dB of stopband attenuation at twice the frequency, compared with a single ended class D amplifier.

16.5 A flexible thin-film pixel array with a charge-to-current gain of 59µA/pC and 0.33% nonlinearity and a cost effective readout circuit for large-area X-ray imaging

An open loop architecture for a reference voltage buffer in ΔΣ-converters is presented to achieve fast-settling, since the settling time of the references plays an important role in the global performance of sampled data converters. This design has been tested on a 2-1 ΔΣ-converter with an on-chip bandgap reference increasing the input related dynamic range up to 93.4 dB for a bandwidth of 99 kHz.