Bram De Muer

On the analysis of /spl Delta//spl Sigma/ fractional-N frequency synthesizers for high-spectral purity

Since /spl Delta//spl Sigma/ Fractional-N synthesis is becoming a popular path to synthesizer integration, thorough analysis is mandatory to uncover its pitfalls. Two generic analysis methods for /spl Delta//spl Sigma/ fractional-N synthesis are presented. The first analysis method is based on linear system theory and provides insight on the fundamental bandwidth limitations imposed by the /spl Delta//spl Sigma/ quantization noise in terms of rms phase error and phase-noise. To swiftly and accurately examine the effect of nonidealities on the spectral purity of the synthesizer, a fast, nonlinear analysis method is developed. Serious in-band noise leakage and reemerging spurious tones can be observed, which are in close correspondence with experimental results. Both methods are applied to distinguish the pros and cons of multistage noise-shaping (MASH) and single-loop /spl Delta//spl Sigma/ modulators in fractional- N synthesis. Based on the analysis methods, practical circuit design guidelines are compiled, with a focus on monolithic /spl Delta//spl Sigma/ fractional-N synthesizer design in CMOS with high spectral purity. These circuit design guidelines are applied to design a monolithic /spl Delta//spl Sigma/-controlled fractional-N phased-locked loop in 0.25-/spl mu/m CMOS that complies to the stringent DCS-1800 cellular specifications, which serves as a test case for experimental verification of the presented analysis methods.

A 1.5W 10V-output Class-D amplifier using a boosted supply from a single 3.3V input in standard 1.8V/3.3V 0.18μm CMOS

In this paper, a complete high-voltage concept is presented, designed in a low- voltage CMOS technology, using only the nominal voltage as input. A test chip has been developed with an inductive DC-DC converter generating a 10V output from a single 3.3V input in a standard 1.8V/3.3V 0.18μm CMOS technology. The generated 10V serves as a supply for an on-chip Class-D output stage, able to deliver 1.5W. The 10V is protected by a custom high-voltage ESD clamp. Reliable operation of the low-voltage devices is guaranteed, including process, power supply and temperature variations, without the need for special startup circuits.

Fully Integrated CMOS Frequency Synthesizers for Wireless Communications

This work presents a design strategy for fully integrated CMOS frequency synthesizers, using the DCS-1800 class I/II standard as driving application. The design of the loop filter is emphasized. The goal is to minimize the integrated capacitance while maintaining the required phase noise and dynamic performance by proper filter topology selection and optimization of the loop parameters. Based on these results, a type-II, fourth-order PLL frequency synthesizer is implemented in a standard 0.25μm CMOS technology, including a monolithic voltage controlled oscillator and a fully integrated loop filter. The measurements show full compliance with the DCS-1800 class I/II specifications, while the occupied area is only 2 × 2 mm2. To conclude, the influence of ∆∑ fractional-N division control on the performance of the PLL frequency synthesizer is discussed.

Monolithic CMOS Fractional-N Frequency Synthesizer Design for High Spectral Purity

Does fractional-N synthesis offer the way out for monolithic CMOS integration of high-quality transceivers? That is the question raised and answered in this document based on the most critical criteria influenced by extending the integer phase-locked loop (PLL) with fractional capabilities: phase noise and spurious tones, i.e. the spectral purity, integratability and agility. Linear system theory is applied to uncover the fundamental bandwidth limitations imposed by the δσ noise in typical PLLs. Practice however proves the linear approach inaccurate. Therefore, a non-linear analysis method is developed, that swiftly predicts the effects of PLL non-linearities on the spectral purity. Serious in-band noise leakage and re-emerging spurious tones can be observed and are in close correspondence with experimental results. Both methods are applied to compare MASH and single-loop δσ modulators in fractional-N synthesis. Based on the analyses, practical circuit design guidelines are compiled and applied to design a monolithic δσ-controlled fractional-N PLL in 0.25μm CMOS that complies to the stringent DCS-1800 cellular specifications.

Low Power RF Power Harvesting Enabling More Active Tag Functionality

This paper presents the analog part of a production integrated circuit (IC) for EPC Gen2 UHF RFID applications in the 900 MHz band. The tag is unique for its on chip 32 kB non-volatile memory (NVM) I2C functionality and its large reading and writing distance. To achieve these goal a power oriented architectural and block level design approach has been followed. The main considerations concerning energy harvesting and RFID communication are presented in this paper and some specific building blocks are more elaborated like a 2.5% accurate clock reference consuming only 0.3 μA and a 6.25 μs TARI ASK demodulator. The chip is currently in production and is going to be used in aviation for airplane parts logging.