Bert Serneels

A high-voltage output driver in a 2.5-V 0.25-/spl mu/m CMOS technology

The design of a high-voltage output driver in a digital 0.25-/spl mu/m 2.5-V technology is presented. The use of stacked devices with a self-biased cascode topology allows the driver to operate at three times the nominal supply voltage. Oxide stress and hot carrier degradation is minimized since the driver operates within the voltage limits imposed by the design rules of a mainstream CMOS technology. The proposed high-voltage architecture uses a switching output stage. The realized prototype delivers an output swing of 6.46 V to a 50-/spl Omega/ load with a 7.5-V supply and an input square wave of 10 MHz. A PWM signal with a dual-tone sinusoid at 70 kHz and 250 kHz results in an IM3 of -65 dB and an IM2 of -67 dB. The on-resistance is 5.9 /spl Omega/.

A 1.5W 10V-output Class-D amplifier using a boosted supply from a single 3.3V input in standard 1.8V/3.3V 0.18μm CMOS

In this paper, a complete high-voltage concept is presented, designed in a low- voltage CMOS technology, using only the nominal voltage as input. A test chip has been developed with an inductive DC-DC converter generating a 10V output from a single 3.3V input in a standard 1.8V/3.3V 0.18μm CMOS technology. The generated 10V serves as a supply for an on-chip Class-D output stage, able to deliver 1.5W. The 10V is protected by a custom high-voltage ESD clamp. Reliable operation of the low-voltage devices is guaranteed, including process, power supply and temperature variations, without the need for special startup circuits.

A 5.5 V SOPA line driver in a standard 1.2 V 0.13 /spl mu/m CMOS technology

In this work a high voltage line driver, using a self-oscillating power amplifier (SOPA) in a digital 1.2 V 0.13 /spl mu/m CMOS technology is presented. A self biasing cascode topology allows the line driver to operate at 4.5 times the nominal supply voltage. Oxide breakdown and hot carrier degradation is minimized since the driver operates within the voltage limits imposed by the design rules of a mainstream CMOS technology. The realized prototype delivers a 35 MHz PWM square wave with a 4.6 V swing in a 7.1 /spl Omega/ load with an efficiency of 62%. The chip achieves a spurious free dynamic range (SFDR) of 52 dB while driving a 1 MHz sine wave. A missing tone power ratio (MTPR) of 50 dB has been measured for a DMT signal up to 1.1 MHz with a crest factor of 14 dB.

A high-voltage output driver in a standard 2.5 V 0.25 /spl mu/m CMOS technology

A robust 7.5 V output driver is realized in standard 2.5 V 0.25 /spl mu/m CMOS. The chip delivers an output swing of 6.46 V to a 50 /spl Omega/ load with a 10 MHz input square wave. A dual-tone PWM signal at 70 kHz and 250 kHz results in an IM3 of -65 dBm. The on-resistance is 5.9 /spl Omega/.

A 237mW aDSL2+ CO Line Driver in Standard 1.2V 0.13μ CMOS

An ADSL2+ CO line driver with a 5.5V output buffer is implemented in a standard 1.2V 0.13mum CMOS technology. The line driver has an MTPR of 58dB and an efficiency of 42% for driving ADSL2+ signals with an average output power of 20dBm and a crest factor of 5.6. The 5.5V output buffer is designed with only digital active CMOS elements without the use of extra masks.

Digital communication systems: the problem of analog interface circuits

Due to the use of deep sub-micron and nano technologies, the signal processing in the digital area becomes so powerful that the limitations are again situated in the analog front-end circuits. This becomes a huge problem in signal output drivers. The development of xDSL and RF systems all lack efficient power amplifiers, especially if they have to be realized in standard CMOS technologies. Another challenge is the design of wide-band receiver front-ends including low-noise input-matched CMOS amplifiers. An overview of the limitations, trends and some recent achievements from the open literature were analyzed and discussed.