Timothy J. Schmerbeck

Modeling Chip/Package Power Distribution

The power bus that interconnects the switching and non-switching functions on the chip is a major source of coupling between widely separated circuits. Switching return currents take the path of least impedance which is often an on-chip path through the power rails. The presence of on-chip decoupling capacitance distributed on the bus can lessen the amount of bus fluctuation due to these switching currents. The simple discussion that follows assumes that the bus is routed on a metal level but busses are often routed or strapped by salicided polysilicon, silicon, or diffused areas as well. Figure 8.1 shows one rail of a power bus in a random or tree power grid structure. There are two switching functions and two non-switching or quiet circuit functions. There is a single chip pad for the supply rail for both switching and non-switching functions. There is on-chip resistive bus drop which provides coupling between switching and non switching functions in addition to the inductive power bounce due to the package inductance connected to the chip power pad. The additional on-chip resistive coupling, which can be substantial, makes this approach usually undesirable. Sometimes additional bus resistance can be beneficial in specific area where it tends to damp RLC ringing of the power bus. The tree power bus scheme usually requires minimum metal area for the bus but must be hand crafted for each design. There is at least one automatic power supply bus routing tool available that routes the bus based on analog signal integrity constraints.[8.13] Figure 8.1

Substrate Modeling in Heavily-Doped Bulk Processes

In Chapter 4 substrate models were developed and discussed that are valid for any process technology in silicon. Additionally, for processes with an epitaxial layer on a heavily-doped bulk (doping density of 1018/cm3 or higher) as is typical of many CMOS technologies, a simpler model can be used-the single node model [6.1],[6.2] In this chapter we will discuss the single-node model, its advantages and limitations and some ways to overcome the latter.

Controlling Substrate Coupling in Heavily-Doped Bulk Processes

The chip substrate acts as a collector and distributor of noise on the IC. The amount of coupling varies depending on the structure and doping of the chip substrate as well as how it is tied to its assigned voltage potential on chip. Essentially every chip voltage transient on chip signal wires, I/O pads, and power rails is capacitively coupled to the chip substrate. This includes energy from card reflections back to I/O pads and transmitted to the substrate via I/O protect devices. Experiments done at IBM and outside have determined that the noise energy coupled to and from the substrate is proportional to the total chip switching power as well as to the logic power rail inductance and chip substrate tie inductance. Coupled noise peak voltages are frequency dependent, unlike the coupled energy, due to constructive and destructive interference of the various frequencies.

Sources of Noise and Methods of Coupling

Clearly the lowest level noise present on semiconductor chips is due to electronic device noise caused by the random movement of charges through resistances, across transistor junctions, and random fluctuations in the charge recombinations in surface states and the semiconductor bulk. The level of noise generated and coupled by thermal noise, avalanche noise, shot noise, and 1/f noise represents a minimum level in coupled noise and all other noise mechanisms treated are usually orders of magnitude worse than these without special design. It is difficult enough to produce an amplifier with a rating of lnano-volt/root Hz or less with device noise alone. Their control is accomplished mainly through optimum circuit design and topology with bandwidth limiting of signals and semiconductor process control. The circuit effects of chip thermal gradients, mechanical or piezoelectric stress, hot electrons effects, and mobile Ionics such as sodium, can be considered very low frequency noise or noise coupling. Their control is usually accomplished with careful consideration of chip isotherms and mechanical stress lines, circuit design and biasing, balanced physical layout, and process control.

Simplified Substrate Modeling and Rapid Simulation

As discussed earlier a semiconductor device simulator is an accurate computer-aided design tool to investigate substrate coupling related behaviour in a mixed-signal environment, although to simulate circuits with more than a few transistors can require overly large amounts of computational time and resources. The use of such a simulator is useful in terms of studying the characteristics of coupling through the substrate in a given process and to obtain direction in terms of strategies to overcome it [4.3]. However, the amount of coupling is extremely layout dependent and can vary dramatically depending on the nature of the substrate biasing and guard ringing employed and also the distribution of the power supplies used to bias the substrate. Consequently, even though layout guidelines can be established and employed to reduce the coupling, it becomes necessary to verify real designs, ranging anywhere in size from a few transistors to hundreds of thousands of them in order to break the expensive cycle of design, layout and fabrication. Thus, mixed-signal designers require a tool that they can use in conjunction with a circuit simulator which will indicate to them signs, if any, of performance deterioration due to substrate noise. Not only does the tool need to be accurate, it must also be fast enough to allow them to use it as many times as is required to optimize a design to meet its performance specifications without sacrificing large amounts of design time.

Semiconductor Device Simulation

One of the available methodologies to simulate substrate coupling is a semiconductor device simulator such as TMA MEDICI [3.2] or MEDUSA [3.4] which employs numerical techniques to analyze semiconductor device action. In this chapter we discuss an overview of such an approach, its significance and its attributes [3.1].

Chip/Package Shielding and Good Circuit Design Practice

It is now occurring that radiated emissions from a single packaged IC are exceeding FCC Class B specifications in the United States as well as other emission standards through-out the world. Violation of radiated emission specifications will usually occur well before the emissions start to functionally perturb the design itself. For radiated Class B designs that have clock frequencies exceeding 100Mhz the specification on the emissions envelope at 5 meters distance from the device extends to 1Ghz in frequency. Class A specifications are taken at 10 meters distance from the radiating device. The usual definition of far field radiated noise is that the distance from source ( > frac{lambda }{{2Pi }} ) Antenna length, L~> λ (wavelength) for an EFFICIENT antenna.A “rule of thumb” to minimize radiated emissions is to keep the chip package linear dimensions ( L < frac{lambda }{{20}} ) and to keep the chip/package ( Area < frac{{{lambda ^2}}}{{800}} ) ▪ An example: n n

A Design Example

lambda = 30cm@f = 1Ghz,frac{{.lambda }}{{2Pi }} approx 4.8cm,frac{lambda }{{20}} approx 1.5cmfrac{{{lambda ^2}}}{{800}} approx 1.125c{m^2}.