Nishath K. Verghese

Addressing substrate coupling in mixed-mode ICs: simulation and power distribution synthesis

This paper describes new techniques for the simulation and power distribution synthesis of mixed analog/digital integrated circuits considering the parasitic coupling of noise through the common substrate. By spatially discretizing a simplified form of Maxwells equations, a three-dimensional linear mesh model of the substrate is developed. For simulation, a macromodel of the fine substrate mesh is formulated and a modified version of SPICE3 is used to simulate the electrical circuit coupled with the macromodel. For synthesis, a coarse substrate mesh, and interconnect models are used to couple linear macromodels of circuit functional blocks. Asymptotic Waveform Evaluation (AWE) is used to evaluate the electrical behavior of the network at every iteration in the synthesis process. Macromodel simulations are significantly faster than device level simulations and compare accurately to measured results. Synthesis results demonstrate the critical need to constrain substrate noise and simultaneously optimize power bus geometry and pad assignment to meet performance targets. >

Verification techniques for substrate coupling and their application to mixed-signal IC design

This paper presents techniques for the analysis of substrate-coupled noise in mixed-signal integrated circuits. Advantages and limitations of some commonly employed verification techniques for substrate coupling are outlined. A preprocessed boundary element method introduced in this paper utilizes precomputed z parameters to generate an analytical model for substrate impedance in a preprocessing stage. Truncated series expansions of the analytical impedance model are used to accelerate solution of the resulting boundary element equations. A methodology that applies these fast techniques to the verification of large mixed-signal circuits and results that confirm its efficiency are described. This complete methodology has been applied to the design and verification of an industrial mixed-signal video analog-to-digital converter IC for substrate noise problems.

Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation

Issues related to substrate noise in system-on-chip design are described including the physical phenomena responsible for its creation, coupling transmission mechanisms and media, parameters affecting coupling strength, and its impact on mixed-signal integrated circuits. Design guidelines and best practices to minimize the generation, transmission, and reception of substrate noise are outlined, and different modeling approaches and computer simulation methods used in quantifying the noise coupling phenomena are presented. Finally, experiments that validate the modeling approaches and mitigation techniques are reviewed

Computer-aided design considerations for mixed-signal coupling in RF integrated circuits

This paper reviews computer-aided design techniques to address mixed-signal coupling in integrated circuits, particularly wireless RF circuits. Mixed-signal coupling through the chip interconnects, substrate, and package is detrimental to wireless circuit performance as it can swamp out the small received signal prior to amplification or during the mixing process. Specialized simulation techniques for the analysis of periodic circuits in conjunction with semi-analytical methods for chip substrate modeling help analyze the impart of mixed-signal coupling mechanisms on such integrated circuits. Application of these computer-aided design techniques to real-life problems is illustrated with the help of a design example. Design techniques to mitigate mixed-signal coupling can be determined with the help of these modeling and analysis methods.

Rapid simulation of substrate coupling effects in mixed-mode ICs

Asymptotic waveform evaluation (AWE) techniques have been used to develop macromodels that allow accurate and efficient simulation of substrate-related parasitic electrical coupling effects using a modified version of SPICE3. While achieving comparable accuracy to a mixed device-circuit simulator (PISCES IIB), simulation time is reduced by several orders of magnitude. The macromodeling technique can be extended to simulate noise coupling in a VLSI chip, in contrast to conventional device-circuit simulators.

Fast parasitic extraction for substrate coupling in mixed-signal ICs

Techniques for the fast extraction of substrate resistances in mixed-signal integrated circuits are presented. For a given process, a simple analytical model for point-to-point substrate impedance is determined during a preprocessing stage. A hierarchical extraction strategy is then employed using this simple analytical model in conjunction with a delimitation technique to quickly determine resistive coupling through the substrate on a cell-by-cell basis. The extraction procedure yields a resistive netlist which when simulated along with necessary parasitic capacitances and the circuit itself determines any performance limitations in the design due to substrate coupling. The extraction procedure has been used in the verification and redesign of a triple 8-bit video A/D converter IC for substrate-noise problems.

SUBTRACT: a program for the efficient evaluation of substrate parasitics in integrated circuits

Algorithms for the efficient evaluation of substrate parasitics in mixed-signal integrated circuits have been developed and incorporated in an extraction tool for substrate parasitics, SUBTRACT. Using a preprocessed, polynomial-based boundary element method, SUBTRACT enables the parasitic extraction process to be completely technology independent, allowing for fast evaluation. Additionally, techniques to accelerate the iterative solution of the resulting impedance matrix have been developed and employed to further improve the speed advantages that this method offers. The preprocessed boundary element method is more efficient than finite-difference schemes and orders of magnitude faster than general boundary element methods using a direct evaluation of Greens function. Results of employing SUBTRACT to the design and verification of a mixed-signal A/D converter IC are described.

Noise considerations for mixed-signal RF IC transceivers

This paper discusses design trade‐offs for mixed‐signal radio frequency integrated circuit (RF IC) transceivers for wireless applications in terms of noise, signal power, receiver linearity, and gain. During air wave transmission, the signal is corrupted by channel noise, adjacent interfering users, image signals, and multi‐path fading. Furthermore, the receiver corrupts the incoming signal due to RF circuit non‐linearity (intermodulation), electronic device noise, and digital switching noise. This tutorial paper gives an overview of the design trade‐offs needed to minimize RF noise in an integrated wireless transceiver. Fundamental device noise and the coupling of switching noise from digital circuits to sensitive analog sections and their impact on RF circuits such as frequency synthesizers are examined. Methods to minimize mixed‐signal noise coupling and to model substrate noise effects are presented.

Modeling Chip/Package Power Distribution

The power bus that interconnects the switching and non-switching functions on the chip is a major source of coupling between widely separated circuits. Switching return currents take the path of least impedance which is often an on-chip path through the power rails. The presence of on-chip decoupling capacitance distributed on the bus can lessen the amount of bus fluctuation due to these switching currents. The simple discussion that follows assumes that the bus is routed on a metal level but busses are often routed or strapped by salicided polysilicon, silicon, or diffused areas as well. Figure 8.1 shows one rail of a power bus in a random or tree power grid structure. There are two switching functions and two non-switching or quiet circuit functions. There is a single chip pad for the supply rail for both switching and non-switching functions. There is on-chip resistive bus drop which provides coupling between switching and non switching functions in addition to the inductive power bounce due to the package inductance connected to the chip power pad. The additional on-chip resistive coupling, which can be substantial, makes this approach usually undesirable. Sometimes additional bus resistance can be beneficial in specific area where it tends to damp RLC ringing of the power bus. The tree power bus scheme usually requires minimum metal area for the bus but must be hand crafted for each design. There is at least one automatic power supply bus routing tool available that routes the bus based on analog signal integrity constraints.[8.13] Figure 8.1

Substrate Modeling in Heavily-Doped Bulk Processes

In Chapter 4 substrate models were developed and discussed that are valid for any process technology in silicon. Additionally, for processes with an epitaxial layer on a heavily-doped bulk (doping density of 1018/cm3 or higher) as is typical of many CMOS technologies, a simpler model can be used-the single node model [6.1],[6.2] In this chapter we will discuss the single-node model, its advantages and limitations and some ways to overcome the latter.