Timothy M. Hancock

A Compressed Sensing Analog-to-Information Converter With Edge-Triggered SAR ADC Core

This paper presents the design and implementation of an analog-to-information converter (AIC) based on compressed sensing. The core of the AIC is an edge-triggered charge-sharing SAR ADC. Compressed sensing is achieved through random sampling and asynchronous successive approximation conversion using the ADC core. Implemented in 90nm CMOS, the prototype SAR ADC core achieves a maximum sample rate of 9.5MS/s, an ENOB of 9.3 bits, and consumes 550μW from a 1.2V supply. Measurement results of the compressed sensing AIC demonstrate effective sub-Nyquist random sampling and reconstruction of signals with sparse frequency support suitable for wideband spectrum sensing applications. When accounting for the increased input bandwidth compared to Nyquist, the AIC achieves an effective FOM of 10.2fJ/conversion-step.

A Compressed sensing analog-to-information converter with edge-triggered SAR ADC Core

This paper presents the design and implementation of an analog-to-information converter (AIC) capable of Nyquist and compressed sensing modes of operation. The core of the AIC is a 10-bit edge-triggered charge-sharing SAR ADC with a figure of merit (FOM) of 55 fJ/conversion-step and Nyquist-sampling rate of 9.5 Msample/s. The integration of a pseudorandom clock generator enables compressed sensing operation via random sampling and subsequent asynchronous successive approximation conversion by the core ADC. The AIC allows complete reconstruction of a spectrum consisting of sparse single tones or sparse frequency bands using compressed sensing algorithms based on ℓ1-minimization as well as ℓ1,2 regularization, which exploits group sparsity. Implemented in 90 nm CMOS, the prototype SAR ADC core achieves a maximum sample rate of 9.5 MS/s, an ENOB of 9.3 bits, and consumes 550 μW from a 1.2 V supply. Measurement results of the AIC demonstrate an effective bandwidth of 25 MHz, which is 5 × greater than Nyquist-sampling rate with an improved effective FOM of 12.2 fJ/conversion-step for signals with sparse frequency support.

Nonreciprocal acoustoelectric interaction of surface waves and fluorine plasma-treated AlGan/GaN 2DEG

This paper demonstrates acoustoelectric (AE) effects for surface acoustic waves (SAWs) propagating in an AlGaN/GaN 2DEG, where a fluorine based plasma has been used to tune the carrier concentration. Incorporation of fluorine ions in the AlGaN barrier is shown to reduce sheet carrier density in the 2D layer, which is required to prevent screening of piezoelectric fields. Tuning of the 2DEG channel is also observed with a progressive shift of the threshold voltage for co-fabricated HEMT structures. The monolithic gain devices exhibit nonreciprocal insertion losses under applied DC bias for higher-order Rayleigh modes in GaN on sapphire at 728 MHz and 1.48 GHz. This constitutes a first step in implementing the carrier control required for AE gain in 2D semiconductors with intrinsically high sheet density.

A Sub-10mW 2Mbps BFSK Transceiver at 1.35 to 1.75GHz

This work presents the design and measurement of a 2 Mbps BFSK transceiver at 1.35 to 1.75 GHz for use in wireless sensor node applications. The receiver is a direct conversion architecture and has a sensitivity of -74 dBm at 2Mbps and consumes 8.0 mW. The transmitter generates orthogonal BFSK modulation through the use of digital pre-emphasis of the synthesizer frequency control word and consumes 9.7 mW including the power amplifier. The transmitter delivers >3 dBm of output power for a total transmitter power efficiency of 23% and a transmitter FOM of 4.85 nJ/bit at 2 Mbps.

A 16mW 8Mbps Fractional-N FSK Modulator at 15.8-18.9GHz

Indirect modulation of fractional-N synthesizers is an energy-efficient architecture capable of moderate data rates, and is well-suited for use in sensor networks or WLAN. Although the architecture is used primarily at low RF frequencies, the capability for fractional-N synthesizers at Ku-band and above currently exist in available silicon technology. Recent demonstrations at 10-25GHz show promising results, although power consumption at this higher frequency remains high for small battery-powered devices. This work implements a fully-integrated fractional-N synthesizer optimized for power efficient modulation at 15.8 to 18.9GHz with an 80MHz reference. Binary and 4-ary FSK modulation of up to 8Mbps is achieved while consuming 16 mW in IBM 0.18 mum SiGe BiCMOS.

Session 22 — High frequency analog techniques

Summary form only given. This session presents analog techniques applied to high-frequency applications found in RF systems & data acquisition systems. The first paper presents a tunable low-pass filter from 34-314 MHz with a 22 dBm IIP3 while consuming only 4.6 mW. The 3rd-order filter is constructed from inverter-based gm-cells and non-linear MOSCAPs, leveraging several distortion cancellation techniques. Additionally the filter resistors and capacitors are used to self-compensate the negative feedback circuits resulting in lower power and a very small circuit area of 0.007 mm2. The second paper presents a tunable RF bandpass filter with Q-tuning implemented in a 0.13 μm SiGe BiCMOS process. The filter is tunable from 2.25-4.5 GHz with independent Q-tuning from 3-150. Linearity is improved by using a dual varactor for tuning such that the varactor 3rd order distortion cancels over the range where the MOS varactors are the most nonlinear. This results in an out-of-band IIP3 of 23.5 dBm. The third paper presents an injection locked PLL (ILPLL) at 2 GHz fabricated in a 65nm CMOS process consuming 3.74 mW form 0.9 V. Traditional ILPLLs use a tunable delay line to inject the reference pulse into the oscillator and require delay line calibration to ensure proper timing of the pulse to minimize the reference spur. In this work, an injection locked frequency divider (ILFD) is used to introduce a phase shift in the feedback path of the ILPLL. This has the effect of locking the delay in the ILPLL to a fixed delay line resulting in a simple, low power calibration that can be run in the background. The fourth and final paper in the session leverages a 0.25 μm GaN HEMT process to implement a high SNR track-and-hold. The T/H provides a 98 dB SNR at 200 MHz for greater than 16-bit performance. The primary challenge in using a GaN process for T/H applications is related to the gate leakage associated with the Schottky contact gate. In this work a gate bootstrapping technique is used as well as a two-stage T/H to minimize droop in hold mode.