Mark A. Gouker

MEMS microswitches for reconfigurable microwave circuitry

The performance is reported for a new microelectromechanical structure (MEMS) cantilever microswitch. We report on both dc- and capacitively-contacted microswitches. The dc-contacted microswitches have contact resistance of less than 1 /spl Omega/, and the RF loss of the switch up to 40 GHz in the closed position is 0.1-0.2 dB. Capacitively-contacted switches have an impedance ratio of 141:1 from the open to closed state and in the closed position have a series capacitance of 1.2 pF. The capacitively-contacted switches have been measured up to 40 GHz with S/sub 22/ less than -0.7 dB across the 5-40 GHz band.

MEMS microswitch arrays for reconfigurable distributed microwave components

A revolutionary device technology and circuit concept is introduced for a new class of reconfigurable microwave circuits and antennas. The underlying mechanism is a compact MEMs cantilever microswitch that is arrayed in two-dimensions. The switches have the ability to be individually actuated. By constructing distributed circuit components from an array, the individual addressability of the microswitch provides the means to reconfigure the circuit trace and, thus, provides the ability to either fine-tune or completely reconfigure the circuit elements behavior. Device performance can be reconfigured over a decade in bandwidth in the nominal frequency range of 1 to 100 GHz. In addition, other circuit-element attributes can be reconfigured such as instantaneous bandwidth, impedance, and polarization (for antennas). This will enable the development of next-generation communication, radar and surveillance systems with agility to reconfigure operation for diverse operating bands, modes, power levels, and waveforms.A novel MEMS switch design for use in microwave circuits is presented. The microswitch is capable of being configured in a multi-element X-Y array for use in tunable distributed circuits. Circuit design concepts using microswitch arrays and measurements of single microswitch performance are given.

Advanced Fabrication Processes for Superconducting Very Large-Scale Integrated Circuits

We review the salient features of two advanced nodes of an 8-Nb-layer fully planarized process developed recently at MIT Lincoln Laboratory for fabricating single flux quantum (SFQ) digital circuits with very large-scale integration on 200-mm wafers: the SFQ4ee and SFQ5ee nodes, where “ee” denotes that the process is tuned for energy-efficient SFQ circuits. The former has eight superconducting layers with 0.5-μm minimum feature size and a 2-Ω/sq Mo layer for circuit resistors. The latter has nine superconducting layers: eight Nb wiring layers with the minimum feature size of 350 nm and a thin superconducting MoNx layer (Tc ~ 7.5 K) with high kinetic inductance (about 8 pH/sq) for forming compact inductors. A nonsuperconducting (Tc <; 2 K) MoNx layer with lower nitrogen content is used for 6-Ω/sq planar resistors for shunting and biasing of Josephson junctions (JJs). Another resistive layer is added to form interlayer sandwich-type resistors of milliohm range for releasing unwanted flux quanta from superconducting loops of logic cells. Both process nodes use Au/Pt/Ti contact metallization for chip packaging. The technology utilizes one layer of Nb/AlOx-Al/Nb JJs with critical current density Jc of 100 μA/μm2 and minimum diameter of 700 nm. Circuit patterns are defined by 248-nm photolithography and high-density plasma etching. All circuit layers are fully planarized using chemical mechanical planarization of SiO2 interlayer dielectric. The following results and topics are presented and discussed: the effect of surface topography under the JJs on the their properties and repeatability, Ic and Jc targeting, effect of hydrogen dissolved in Nb, MoNx properties for the resistor layer and for high-kinetic-inductance layer, and technology of milliohm-range resistors.

Fabrication Process and Properties of Fully-Planarized Deep-Submicron Nb/Al–

A fabrication process for Nb/Al-AlOx/Nb Josephson junctions (JJs) with sizes down to 200 nm has been developed on a 200-mm-wafer tool set typical for CMOS foundry. This process is the core of several nodes of a roadmap for fully-planarized fabrication processes for superconductor integrated circuits with 4, 8, and 10 niobium layers developed at MIT Lincoln Laboratory. The process utilizes 248 nm photolithography, anodization, high-density plasma etching, and chemical mechanical polishing (CMP) for planarization of SiO2 interlayer dielectric. JJ electric properties and statistics such as on-chip and wafer spreads of critical current, Ic, normal-state conductance, GN, and run-to-run reproducibility have been measured on 200-mm wafers over a broad range of JJ diameters from 200 nm to 1500 nm and critical current densities, Jc, from 10 kA/cm2 to 50 kA/cm2 where the JJs become self-shunted. Diffraction-limited photolithography of JJs is discussed. A relationship between JJ mask size, JJ size on wafer, and the minimum printable size for coherent and partially coherent illumination has been worked out. The GN and Ic spreads obtained have been found to be mainly caused by variations of the JJ areas and agree with the model accounting for an enhancement of mask errors near the diffraction-limited minimum printable size of JJs. Ic and GN spreads from 0.8% to 3% have been obtained for JJs with sizes from 1500 nm down to 500 nm. The spreads increase to about 8% for 200-nm JJs. Prospects for circuit densities > 106 JJ/cm2 and 193-nm photolithography for JJ definition are discussed.

\hbox{AlO}_{\rm x}\hbox{/Nb}

Inductance of superconducting thin-film inductors and structures with linewidth down to 250 nm has been experimentally evaluated. The inductors include various striplines and microstrips, their 90° bends and meanders, interlayer vias, etc., typically used in superconducting digital circuits. The circuits have been fabricated by a fully planarized process with 8 niobium layers, developed at MIT Lincoln Laboratory for very-large-scale superconducting integrated circuits. Excellent run-to-run reproducibility and inductance uniformity of better than 1% across 200-mm wafers have been found. It has been found that the inductance per unit length of stripline and microstrip line inductors continues to grow as the inductor linewidth is reduced deep into the submicron range to the widths comparable to the film thickness and magnetic field penetration depth. It is shown that the linewidth reduction does not lead to widening of the parameter spread due to diminishing sensitivity of the inductance to the linewidth and dielectric thickness. The experimental results were compared with numeric inductance extraction using commercial software and freeware, and a good agreement was found for 3-D inductance extractors. Methods of further miniaturization of circuit inductors for achieving circuit densities> 106 Josephson junctions per cm2 are discussed.

Josephson Junctions for VLSI Circuits

A consistent set of figures-of-merit is proposed for the standard characterization of spatial and quasioptical power-combined arrays. A new figure-of-merit, the effective transmitter power, is presented along with slightly modified definitions of standard figures-of-merit. The definitions of these figures-of-merit have been chosen to more directly compare the performance of spatial and quasioptical power-combined arrays with one another and with conventional circuit power-combined transmitters and amplifiers. >

Inductance of Circuit Structures for MIT LL Superconductor Electronics Fabrication Process With 8 Niobium Layers

A fabrication process has been developed for fully planarized Nb-based superconducting interlayer connections (vias) with minimum size down to 250 nm for superconductor very large scale integrated (VLSI) circuits with 8 and 10 superconducting layers on 200-mm wafers. Instead of etched contact holes in the interlayer dielectric it employs etched and planarized Nb pillars (studs) as connectors between adjacent wiring layers. Detailed results are presented for one version of the process that utilizes Nb/Al/Nb trilayers for each wiring layer instead of single Nb wiring layers. Nb studs are etched in the top layer of the trilayer to provide vertical connections between the wires etched in the bottom layer of the trilayer and the next wiring layer that is also deposited as a Nb/Al/Nb trilayer. This technology makes possible a dramatic increase in the density of superconducting digital circuits by reducing the area of interconnects with respect to presently utilized etched contact holes between superconducting layers and by enabling the use of stacked vias. Results on the fabrication and size dependence of electric properties of Nb studs with dimensions near the resolution limit of 248-nm photolithography are presented in the normal and superconducting states. Superconducting critical current density in the fabricated stud-vias is about 0.3 A μm−2 and approaches the depairing current density of Nb films.

Toward standard figures-of-merit for spatial and quasi-optical power-combined arrays

We describe the design and measurement of a hybrid-circuit, tile-approach subarray for use in spatial power-combined transmitters. The subarray consists of 16 monolithic millimeter-wave integrated circuit (MMIC) amplifiers, each feeding a circularly polarized cavity-backed microstrip antenna. The average performance across the 43.5-45.5 GHz band is as follows: EIRP 18.3 dBW, DC-RF efficiency 10.3%, effective transmitter power 530 mW, system gain 13.2 dB, and combining efficiency of 46.2%. The minimum axial ratio is 1.2 dB at 43.9 GHz, and the array has a 3% 3-dB axial ratio bandwidth.

Deep sub-micron stud-via technology of superconductor VLSI circuits

Three designs for a 4-by-4 subarray are described for use in a spatial power-combined transmitter. The subarrays are constructed using a hybrid-circuit, tile-approach architecture and are composed of 16 cavity-backed, proximity-coupled microstrip antennas, each fed by a 0.5 watt amplifier. Both linearly and circularly polarized subarrays have been constructed for operation over a 10% band centered at 10 GHz. The linearly polarized subarray showed the following peak performance: EIRP greater than 27 dBW, effective transmitter power greater than 5 watts, DC-RF efficiency greater than 20%, and excellent graceful degradation performance.

45-GHz MMIC power combining using a circuit-fed, spatially combined array

The precision MCM process described in this paper has several performance enhancing features not found in other reported MCM processes. The process enables the fabrication of inductors with orders of magnitude greater inductance than other packaging techniques for the same area on the MCM.