Timothy M. Hollis

Data Bus Inversion in High-Speed Memory Applications

Efforts to reduce high-speed memory interface power have led to the adoption of data bus inversion or bus-invert coding. This study compares two popular algorithms, which seek to limit the number of simultaneously transitioning signals and bias the state of transmitted data toward a preferred binary level, respectively. A new algorithm, which provides a compromise between transition frequency and preferred signal level, is proposed, and the three algorithms are compared in terms of their impact on power consumption, power supply noise reduction, and general signal integrity enhancement when used in conjunction with a variety of link topologies.

Reference Voltage Generation for Single-Ended Memory Interfaces

While most aspects of single-ended signaling inter- faces do not change from one generation to the next, certain topological changes may enhance the robustness of single-ended schemes at higher datarates. Reference voltage (VREF ) genera- tion is critical to maintaining sufficient signaling margins and thus demands attention. This paper discusses VREF generation and introduces a VREF architecture which provides static level tuning while tracking dynamic power supply variation.

Self-calibrating continuous-time equalization with multiple degrees of freedom

A method for designing self-calibrating continuous-time equalizers is proposed. A pair of error terms, derived from the channel pulse response, may be used to adaptively calibrate the equalizer, resulting in a significant reduction of inter-symbol interference (ISI). Matlab simulations show the clear opening of a twenty Gigabit/second (Gb/s) data eye at the end of a six inch FR4-based signal route.

Jittery Signal Generation for High-Speed Interconnect Simulation

By generating clock and data waveforms in the frequency domain through a truncated Fourier series, absolute control over both voltage noise and symbol transition timing is achieved. A parameterized Fourier series signal model is derived and used to form clock and data waveforms exhibiting arbitrary noise and jitter characteristics. The method not only facilitates more accurate interconnect modeling in tools like Matlab and Simulink, but also provides a simple means for generating realistic signals that may be imported into Spice-based simulators.