Timothy S. Cale

Von Mises Stress in Chemical‐Mechanical Polishing Processes

In this paper we (i) describe a model for the stress distribution across a wafer during chemical-mechanical polishing, which is solved using I-DEAS (a commercial software package) and (ii) summarize the predicted effects of carrier film and pad compressibility on polishing nonuniformity. Results indicate that (i) the Von Mises stress correlates with polishing nonuniformity, while the normal stress does not correlate with the nonuniformity and (ii) CMP uniformity improves with decreasing polishing pad and carrier film compressibility.

Stress distribution in chemical mechanical polishing

Abstract This paper describes a first principles, three-dimensional, wafer scale model that relates chemical mechanical polishing (CMP) non-uniformity (NU) to the distribution of Von Mises stress on the wafer surface. The model describes mechanical aspects of the polishing process including the effects of down pressure and the physical properties of the carrier, carrier film, wafer and pad. The finite element model is solved using ANSYS (Version 5.2, ANSYS Inc.) to obtain the Von Mises stress distributions. The calculated Von Mises stress distributions correlate well with observed removal rate ( RR ) profiles obtained during oxide polishing. Analysis of the model predictions reveals that the applied down force causes radial deformation of the pad and carrier film during polishing. This deformation induces radial and angular ( θ ) stresses on the wafer surface, and these stresses account for the variation in the calculated Von Mises stress.

Multiscale material removal modeling of chemical mechanical polishing

Abstract This paper describes a multiscale model for material removal during conventional chemical mechanical polishing (CMP). Three spatial scales are considered in the integrated model: (i) abrasive particle scale; (ii) asperity scale; (iii) wafer scale. The model is based on the deformation of hyper-elastic asperities attached to a linear-elastic pad. ANSYS is used to perform finite element analyses of a single asperity to obtain the relations between the deformation of the asperity, and the contact stress and area. Those relations are used in an extended Greenwood–Williamson model to compute the local average contact pressures on the pad. The material removal model includes the abrasive wear caused by local contact stress between the abrasive particles and the wafer, the distribution of asperity heights, and the plastic deformation of the wafer. The material removal rate results for unpatterned wafers are used to predict the material removal rates on a feature. The results of a computer simulation of material removal and the time evolution of a feature are shown. Two FEM based codes, ANSYS and EVOLVE are used; the former for the contact stress analysis and the latter to generate a new surface.

Nanoplate elasticity under surface reconstruction

Using classical molecular statics simulations, we show that nanoplate elasticity strongly depends on surface reconstruction and alignment of bond chains. Because of its well-established surface reconstructions and the readily available interatomic potential, diamond-cubic silicon is the prototype of this study. We focus on silicon nanoplates of high-symmetry surfaces, {111} and {100}; with 7×7 and 2×1 reconstructions. Nanoplates with unreconstructed {111} surfaces are elastically stiffer than bulk. In contrast, the same nanoplates with 7×7 reconstructed {111} surfaces are elastically softer than bulk. On {100} surfaces, the 2×1 surface reconstruction has little impact. The bond chains are along one of the two ⟨110⟩ directions, making the two ⟨110⟩ directions nonequivalent. The alignment of the bond chains on the opposite surfaces of a nanoplate dictates its elastic anisotropy. The sensitivity of nanoplate elasticity on details of surface atomic arrangements may impact the application of nanoplates (or nan...

Multiple scale integrated modeling of deposition processes

The ability to predict feature profile evolution across wafers during processing using equipment scale operating conditions is one important goal of process engineers. We present an integrated approach for simulating the multiple length scales needed to address this problem for thermal chemical vapour deposition (CVD) processes. In this approach, continuum models on the reactor scale and mesoscopic scales are coupled tightly with ballistic transport models on the feature scale to predict micro and macro loading effects in a transient environment. As an example of this approach, the transient simulation results for thermal deposition of silicon dioxide from tetraethoxysilane (TEOS) are presented. The efficiency of the approach presented and extensions to more complex systems are briefly discussed.

A Multiscale Simulator for Low Pressure Chemical Vapor Deposition

An integrated simulator for chemical vapor deposition is introduced. In addition to reactor scale and feature scale simulators, it includes a mesoscopic scale simulator with the typical length scale of a die. It is shown that the three-scale integrated simulator used is a proper extension of two-scale deposition simulators that consist of reactor scale and feature scale simulation models. Moreover, it is demonstrated that information is provided on a new length scale, for which no information is available from the two-scale approach, as well as important corrections to the simulation results on the reactor scale. This enables, for instance, studies of microloading. Thermally induced deposition of silicon dioxide from tetraethyoxysilane is chosen as the application example. The deposition chemistry is modeled using six gaseous reacting species involved in four gas-phase and eight surface reactions.

The role of oxygen excitation and loss in plasma‐enhanced deposition of silicon dioxide from tetraethylorthosilicate

The deposition rate of silicon dioxide from tetraethylorthosilicate/O2 capacitively coupled plasmas increases with increasing applied rf power, increasing total pressure and decreasing wafer temperature. These measured deposition rate dependences can be explained by a simple plasma deposition model in which deposition occurs through both an ion‐assisted and an oxygen atom initiated pathway. The relative contributions of these pathways were roughly isolated using limiting step coverage measurements on low aspect ratio trenches. Limiting step coverages decreased, and hence directionality increased, with increasing rf power density, decreasing total pressure, and increasing wafer temperature. A simple bulk plasma chemistry model combined with an analytical sheath model was developed to qualitatively explain our experimental findings. The model suggests that the ion‐enhanced deposition rate is directly proportional to oxygen ion flux, with a reactive sticking coefficient approaching unity. Using literature va...

Adhesive Wafer Bonding Using Partially Cured Benzocyclobutene for Three-Dimensional Integration

Wafer-level three-dimensional integration (3D) is an emerging technology to increase the performance and functionality of integrated circuits (ICs), with adhesive wafer bonding a key step in one of the attractive technology platforms. In such an application, the dielectric adhesive layer needs to be very uniform, and precise wafer-to-wafer alignment accuracy (similar to 1 mu m) of the bonded wafers is required. In this paper we present a new adhesive wafer bonding process that involves partially curing (cross-linking) of the benzocyclobutene (BCB) coatings prior to bonding. The partially cured BCB layer essentially does not reflow during bonding, minimizing the impact of inhomogeneities in BCB reflow under compression and/or any shear forces at the bonding interface. The resultant nonuniformity of the BCB layer thickness after wafer bonding is less than 1% of the average layer thickness, and the wafers shift relative to each other during the wafer bonding process less than 1 mu m (average) for 200 mm diameter wafers. When bonding two silicon wafers using partially cured BCB, the critical adhesion energy is sufficiently high (>= 14 J/m(2)) for subsequent IC processing.

Modeling Thermal Stresses in 3-D IC Interwafer Interconnects

We present a finite-element-based analysis to determine if there are potential reliability concerns due to thermally induced stresses in interwafer copper via structures in three-dimensional (3-D) ICs when benzocyclobutene (BCB) is used as the dielectric adhesive to bond wafers. We first partially validate our approach by comparing computed results against two types of experimental data from planar ICs: 1) volume-averaged thermal stresses measured by X-ray diffraction in an array of parallel Cu lines passivated with TEOS and 2) studies of failures induced by thermal cycling via chain structures embedded in SiLK or SiCOH. In the volume-averaged thermal stress study, predicted stress slopes (dsigma/dT) agree well with other modeling results. Our computed stress slopes agree reasonably well with experimental data along the Cu line direction and normal to the Cu lines surface, but we underestimate the stress slope across the Cu line. In the case of via chains, computed von Mises stresses agree with the results of thermal cycle experiments; we predict failure when SiLK is used as a dielectric and predict no failure when SiCOH is used as the dielectric. The approach is then employed to study thermal stresses in interwafer Cu vias in 3-D IC structures bonded with BCB. Simulations show that the von Mises stresses in interwafer Cu vias decrease with decreasing pitch at constant via size, increase with decreasing via size at constant pitch, and decrease with decreasing BCB thickness. We conclude that there is a concern regarding the stability of interwafer Cu vias. Guidelines for design parameter values are estimated, e.g., interwafer via size, pitch, and BCB thickness. For 2.6-mum-thick BCB, computations indicate that via size should be larger than 3 mum at a pitch of 10 mum to avoid plastic yield of Cu vias

Free molecular transport and deposition in cylindrical features

A Clausing‐like integral equation is derived which applies to both low pressure chemical vapor deposition (CVD) and physical vapor deposition (PVD) in cylindrical contact holes; i.e., over the full range of sticking coefficient (0–1). A steady state assumption is implicit in the formulation. In the absence of film deposition, the flux to the surface is spatially uniform. Analytical expressions are presented for the initial deposition profiles for PVD (unity sticking coefficient). Numerical inversions of the integral equations provide initial deposition profiles for CVD (low sticking coefficients). Initial deposition profiles exhibit poor uniformity in PVD and high uniformity in CVD, in agreement with empirical evidence. The results provide a test for proposed Monte Carlo simulations which are based on the same assumptions.