Max O. Bloomfield

Modeling Thermal Stresses in 3-D IC Interwafer Interconnects

We present a finite-element-based analysis to determine if there are potential reliability concerns due to thermally induced stresses in interwafer copper via structures in three-dimensional (3-D) ICs when benzocyclobutene (BCB) is used as the dielectric adhesive to bond wafers. We first partially validate our approach by comparing computed results against two types of experimental data from planar ICs: 1) volume-averaged thermal stresses measured by X-ray diffraction in an array of parallel Cu lines passivated with TEOS and 2) studies of failures induced by thermal cycling via chain structures embedded in SiLK or SiCOH. In the volume-averaged thermal stress study, predicted stress slopes (dsigma/dT) agree well with other modeling results. Our computed stress slopes agree reasonably well with experimental data along the Cu line direction and normal to the Cu lines surface, but we underestimate the stress slope across the Cu line. In the case of via chains, computed von Mises stresses agree with the results of thermal cycle experiments; we predict failure when SiLK is used as a dielectric and predict no failure when SiCOH is used as the dielectric. The approach is then employed to study thermal stresses in interwafer Cu vias in 3-D IC structures bonded with BCB. Simulations show that the von Mises stresses in interwafer Cu vias decrease with decreasing pitch at constant via size, increase with decreasing via size at constant pitch, and decrease with decreasing BCB thickness. We conclude that there is a concern regarding the stability of interwafer Cu vias. Guidelines for design parameter values are estimated, e.g., interwafer via size, pitch, and BCB thickness. For 2.6-mum-thick BCB, computations indicate that via size should be larger than 3 mum at a pitch of 10 mum to avoid plastic yield of Cu vias

Integrated multiscale process simulation

Abstract We summarize two approaches to integrated multiscale process simulation (IMPS), particularly relevant to integrated circuit (IC) fabrication, in which models for equipment (m) and feature (μm) scales are solved simultaneously. The first approach uses regular grids, and is applied to low-pressure chemical vapor deposition (LPCVD) of silicon dioxide from tetraethoxysilane (TEOS). The second approach uses unstructured meshes, and is applied to electrochemical deposition (ECD) of copper. The goal is to develop approaches to estimate “loading” in these processes; i.e., the effects of pattern density and topography on local deposition rates. This is accomplished by resolving pattern (mesoscopic, mm) scales, which are between equipment (0.1–1 m) and feature scales (0.1–1 μ m). In this work, we focus on steady-state simulation results. We close with a few thoughts on extending IMPS to the grain scale, and the conversion of discrete atomistic representations to continuum representations of islands during deposition.

Modeling pattern density dependent bump formation in copper electrochemical deposition

A model and simulator that describe the dependence of deposition rate and bump formation on pattern density during electrochemical deposition (ECD) are presented. A curvature-enhanced ECD model from the recent literature [A.C. West et al., Electrochem. Solid-State Lett., 4. C50, (2001)] is used in a feature scale process simulator to explain bump formation and to qualitatively explain some observed pattern density effects. Experimentally, it is known that ECD topographies can be different when features are clustered together compared to isolated features. Although it is difficult to experimentally quantify the extent of bumping over patterned regions of wafers, the curvature-based models for bumping are at least qualitatively consistent with reported trends in deposit shape with feature density.

A computational framework for modelling grain-structure evolution in three dimensions

We describe a simulation framework designed to track individual grains in a material during simulations of formation, processing and usage. The framework, which we call parallel level-set environment for nanoscale topography evolution, is designed to fill the clear and present need to account for grain structure in understanding and predicting the performance of structures in some products, such as metal lines in integrated circuits. It is the realization of ‘grain continuum’ models of films by Cale et al. and can be used to complement discrete atomistic simulations and to link them to continuum simulations. We demonstrate the use of multiple level-set methods to track islands nucleated on substrates, during growth and impingement to form a polycrystalline film. Individual grains in the film are defined in the finite-element data structure. We briefly discuss how this simulation tool might be used in an integrated multiscale process simulation environment previously described by Bloomfield et al. to establish a link from atomistic simulations upwards to feature-, pattern- and reactor-scale simulations.

Extension velocities for level set based surface profile evolution

Topography simulations are widely used in the microelectronics industry to study the evolution of surface profiles during such processes as deposition or etching. Comparisons between simulations and experiments are used to test proposed transport and chemistry models. The method used to move the surface (the moving algorithm) should not interfere with this testing process; i.e., it should not introduce artifacts. The reference method, shown to be accurate by several groups in many studies, is conservation law based “front tracking.” Level set approaches are being increasingly used, largely for their robustness to topological changes. They have not been tested against front tracking to determine their accuracy. In this article, we present guidelines on the use of level set methods for two-dimensional surface evolutions as commonly used. Specifically, we deal with two major issues with level set algorithms: the need for “extension velocities” and the rounding of sharp corners due to contouring. We also deal...

The use of conformal voxels for consistent extractions from multiple level-set fields

We present and analyze in 2D an algorithm for extracting self-consistent sets of boundary representations of interfaces from level set representations of many phase systems. The conformal voxel algorithm which is presented requires the use of a mesh generator and is found to be robust and effective in producing the extractions in the presence of higher order junctions.

Thermomechanical behavior of EUV pellicle under dynamic exposure conditions

The utilization of EUV pellicles as protective layers for EUV masks requires the use of refractory materials that can tolerate large temperature excursions due to the non-negligible absorption of EUV radiation during exposure. Additionally, the mechanical stress induced on the EUV pellicle by the thermal load is dependent on the thermal expansion of the material which can be responsible for transient wrinkling. In this study, an ultrathin (20 nm), free-standing membrane based on silicon nitride is utilized as a learning vehicle to understand the material requirements of EUV pellicles under dynamic exposure conditions that are typical of commercial EUV scanners. First, the nanoscale radiative properties (emissivity) and thermo-mechanical failure temperature of the dielectric film under vacuum conditions are experimentally investigated utilizing a pulsed ArF (193 nm) probing laser. The silicon nitride membrane is found to be marginally compatible with an equivalent 80W EUV source power under steady state illumination conditions. Next, the thermal behavior of the EUV pellicle under dynamic exposure conditions is simulated using a finite element solver. The transient temperature profile and stress distribution across the membrane under stationary state conditions are extracted for an equivalent 60W EUV power source and the pellicle wrinkling due to heating and consequent impact on CD uniformity is estimated. The present work provides a generalized methodology to anticipate the thermal response of a EUV pellicle under realistic exposure conditions.

Modeling and simulation of plasma enhanced processing for integrated circuit fabrication

Plasma processes are used extensively in deposition and etching operations used in the fabrication of integrated circuits (ICs). Modeling and simulation studies have helped improve our understanding and process design of several plasma enhanced processes. We use three examples to show that simple chemical and transport models can help with process understanding and process development. Calibration of these simple engineering models is needed, but the approach can provide timely information for engineering level decisions. In the first example we show that simple models for plasma enhanced chemical vapor deposition (PECVD) of silicon dioxide from tetraethoxysilane (TEOS) were useful for several different process designs. Reactive ion etching (RIE) is another common IC fabrication process, and our second example shows how modeling revealed that one potential reason for aspect ratio dependent etching is the interaction between chemistry and transport. Finally, we show how modeling was used in support of process integration to help decide between two proposed process sequences involving deposition, etching and reflow processes.

Component-based workflows for parallel thermomechanical analysis of arrayed geometries

Component-based simulation workflows can increase the agility of the design process by streamlining adaptation of new simulation methods. We present one such workflow for parallel unstructured mesh-based simulations and demonstrate its usefulness in the thermomechanical analysis of an array of solder joints used in microelectronics fabrication. We automate the simulation process from problem specification to the solution of the underlying PDEs, including problem setup, domain definition, and mesh generation. We establish the utility of the proposed approach by demonstrating that qualitatively different stress concentrations are seen in solder joints near the center of such an array and a solder joint seen at the edge of the same array.

Strain Energy Driven and Curvature Driven Grain Boundary Migration in 3D-IC Cu Vias

We use grain-focused models to study grain boundary (GB) migration (GBM) in polycrystalline Cu vias that interconnect MLM layers in 3D ICs. Curvature-driven GB velocities are calculated by PLENTE [1]–[3] using the local mean curvature of the GBs, as described in Ref. 2. We use Comsol Multiphysics [4] to calculate GB velocities due to thermally induced strain energy jumps across GBs [5]. The thermo-mechanical calculations needed for this are made using model structures that combine continuum models and grain-continuum (GC) models (see [1]–[3], [5]); we call these ‘hybrid’ grain-continuum (HGC) models. Curvature driven GB dominates in this work; however, there are uncertainties in the absolute stress values used and how the relative magnitudes of these phenomena will change as the structure evolves.