Tingcun Wei

Design and Characteristics of an Integrated Multichannel Ramp ADC Using Digital DLL Techniques for Small Animal PET Imaging

This paper presents a novel design of an integrated 12-bit multi-channel single-slope ramp analog-to-digital converter (ADC) for a small animal positron emission tomography(PET) imaging system. The proposed ADC is a part of a monolithic front-end readout application-specific integrated circuit(ASIC) which is dedicated to the detector modules consisting of LYSO scintillation crystals read out on both sides by the multi-channel plate (MCP) photodetectors. The function of the ADC is to digitize the voltage signals from a large number of readout channels. Digital delay-locked loop (DLL) techniques are proposed to realize time interpolations in order to reduce the conversion time and to enhance the resolution. Both high precision and low power are obtained. An eight-channel prototype chip is implemented in AMS 0.35 μm CMOS technology. The available resolution of the ADC is 9 ~ 12 bits. The maximum DNL and INL of the fine conversion in the ADC is ±0.75 LSB and ±0.5 LSB, respectively. The static power consumption of the ADC is 3 mW + 0.2 mW/Channel. This ADC architecture provides a possibility to integrate low-noise front-end readout circuits, time-to-digital converters and ADC together into a monolithic ASIC and to output both the energy quantity and the time information with digital representations for PET imaging systems.

Design of a monolithic multichannel front-end readout ASIC for PET imaging based on scintillation crystals read out by photodetectors at both ends

This paper presents the design techniques of a monolithic multichannel front-end readout chip integrated with both high-accuracy TDC and high-resolution ADC for the PET using LYSO(Ce) crystals read out by MCP PMT at both ends. In the front-end readout chain, a regulated cascade (RGC) preamplifier is employed in every channel for amplifying the current signals generated from MCP detector. A gain-adjustment stage, an integrator and a pulse shaper are employed for pulse height analysis which changes the width of the pulses. A discriminator is placed after the preamplifier to generate triggers. These triggers are sent to a sub-nanosecond TDC for measurement and digitizing. The peak values of the shaped pulses are digitized by a multichannel time-based ADC for measurement. Three prototype chips are designed in AMS 0.35 μm CMOS technology. In the front-end readout prototype chip, the dynamic range, the linearity, and the power dissipation are optimized. The input dynamic range from few fC to more than 100 pC can be achieved. The analog output range of the front-end readout circuits is from 1.2 V to 3.2 V. The shaping time is 280 ns and the power dissipation is reduced to less than 15 mW. In the TDC chip based on a DLL array, the RMS jitter and the peak-to-peak jitter of the used DLL are reduced to 7 ps and 21 ps, respectively. The bin size of the TDC has been reduced to 71ps with a reference clock of 100 MHz. In the multichannel time-based ADC chip, a maximum resolution of 12 bits, a sampling rate of ∼1 MS/s, and the power dissipation of 3 mW ° 0.2 mW/channel are achieved.

A 12-bit 2.5MS/s multi-channel ramp Analog-to-Digital Converter for Imaging detectors

This paper presents a 12-bit multi-channel ramp Analog-to-Digital Converter (ADC) for Imaging detectors dedicated to high-energy physics and biomedical imaging applications. A two-level conversion scheme is employed to reduce the conversion time. The conventional Wilkinson-type architecture with a 5-bit Gray counter is used for coarse conversion while a multiphase sampling technique is proposed for fine conversion. An array of delay-locked loop is designed to generate 140-phase clocks so as to achieve a fine resolution of 7-bit. A one-channel prototype chip is designed in 0.35 µm CMOS technology. The maximum conversion time is measured as about 400 ns, which corresponds to a sample rate of about 2.5 MS/s. The power dissipation is about 3mW/channel.

Digitally Current Controlled DC-DC Switching Converters Using an Adjacent Cycle Sampling Strategy

A novel digital current control strategy for digitally controlled DC-DC switching converters, referred to as Adjacent Cycle Sampling (ACS), is proposed in this paper. For the ACS current control strategy, the available time interval from sampling the current to updating the duty ratio, is approximately one switching cycle. In addition, it is independent of the duty ratio. As a result, the contradiction between the processing speed of the hardware and the transient response speed can be effectively relaxed by using the ACS current control strategy. For digitally controlled buck DC-DC switching converters with trailing-edge modulation, digital current control algorithms with the ACS control strategy are derived for three different control objectives. These objectives are the valley, average, and peak inductor currents. In addition, the sub-harmonic oscillations of the above current control algorithms are analyzed and eliminated by using the digital slope compensation (DSC) method. Experimental results based on a FPGA are given, which verify the theoretical analysis results very well. It can be concluded that the ACS control has a faster transient response speed than the time delay control, and that its requirements for hardware processing speed can be reduced when compared with the deadbeat control. Therefore, it promises to be one of the key technologies for high-frequency DC-DC switching converters.

A new differential measurement scheme for projected-capacitive touch controller

For sake of lightness, thinness and low cost, single-layer projected-capacitive touch panel is popular for electronic products. The interference from liquid crystal display in single-layer touch screens is more serious than that in two-layer touch screens. For touch controller IC, differential measurement, which provides high common mode noise rejection, can be used in this case in order to suppress the interference. However, the differential measurement is sensitive to the self-capacitance variation besides the mutual-capacitance variation. As a result, “ghost points” exist in multi-touch application. In order to distinguish the “ghost points”, a new differential measurement scheme is proposed in this paper. By applying complementary excitations on two adjacent drive electrodes, the new measurement scheme only responses to mutual-capacitance variation. A controller IC has been designed based on the proposed scheme in a 0.35 μm 5V CMOS process. The simulation results show that the new scheme effectively solved the problem of “ghost point”. In addition, perfect conversion linearity between mutual capacitance variation and the PGA output voltage is obtained. The touch controller IC in this paper is being fabricated, and the test results are expected in the near future.

Advances in front-end readout ASIC design for PET imaging

This paper presents the advances in design techniques of front-end ASICs for PET imaging applications. The Overview of PET front-end electronics and their features are firstly given. Secondly, the survey of the front-end ASICs dedicated to different kinds of photodetectors, signal acquisitions and imaging strategies is presented. Thirdly, the trends in the design of front-end ASICs are described. The front-end readout and analog signal processing will be replaced by digital methods via a imaging specific DSP. For the future developments, the design of front-end ASIC will focus on the one-chip solution of front-end readout circuits, high-speed digitizers and DSPs. Both hardware techniques and software skills should be employed for the front-end microelectronics system design.

Design of a Touch Controller for Multitouch Screen System With Touch Prediction and Window Sensing (TPWS) Strategy

The touch prediction and window sensing (TPWS) strategy is an effective approach to realize low-cost and low-power multitouch screen systems, especially for large-sized touch screen panels. The structures of traditional touch controller using charge integrating amplifier is not suitable for the TPWS touch screen systems. This paper presents a new touch controller, which is designed for the TPWS touch screen systems and is emphasized to improve the SNR and reporting rate of system. The differential measurement scheme with a full driving method is proposed to eliminate the influences on the SNR and the reporting rate of system caused by the LCD noise, the charger noise and the signal transmission delay on Indium-Tin Oxide (ITO) electrodes. The designed touch controller is realized in a 0.13 µm 1.8 V/5 V embedded flash CMOS process with the chip size of 2.5 × 2.8 mm2. The test results demonstrate that this touch controller supports the TPWS strategy very well and its performances are improved significantly. Comparing with the previous design, the SNR is improved from 25 to 36 dB, and the reporting rate is increased from 83 to 120 Hz.

A reference voltage programmable 6-bit differential delay-line ADC for digitally controlled DC-DC switching converters

This paper presents the design of a 6-bit, 25 Msps, reference voltage programmable delay-line Analog-to-Digital Converter (ADC), which is aimed to use in the digitally controlled DC-DC switching converters. A new differential bias circuit is used to improve the linearity of delay cells and also the ADC. The reference voltage can be adjusted from 1.8 V to 2.5 V with 0.2 V step, and the input voltage range is limited within ±200mV around the reference voltage. This ADC is implemented in 0.18um CMOS process and works at 3.3 V power supply. The simulation results for this ADC show that, the power dissipation is 450 uW, ENOB is 5.96-bit, DNL and INL is less than ±0.55 LSB and ±0.42 LSB, respectively. The designed ADC has the power-and die area-efficiency, it can be used as the built-in ADC of the digital controller in the digitally controlled DC-DC switching converters.

Digital proportional derivative control with steady-state error elimination for DC-DC switching converter

In this paper, a novel digital proportional derivative (D-PD) control algorithm combined with steady-state error elimination is proposed for digitally controlled DC-DC switching converters. The system steady-state error due to the absence of integral in D-PD is eliminated by a register-based error-shift technique without increasing hardware circuit scale. Compared with the digital proportional integral derivative (D-PID) control, proposed control algorithm has fast transient response speed and small overshoot, and also it is easily implemented by hardware circuit as compared with the fuzzy and non-linear control. The design method of voltage compensator in z-domain is given, and the experimental results based on FPGA are provided, which have verified the theoretical analysis results very well. It can be concluded that, the proposed D-PD control algorithm with steady-state error elimination has the advantages of better transient performances and easier hardware implementation simultaneously over the existed control algorithms, therefore it can be used for voltage feedback control in digitally controlled DC-DC switching converters.

Design of a novel 12-bit 1MS/s charge redistribution SAR ADC for CZT detectors

This paper presents a novel design of a 12-bit 1MS/s SAR (Successive Approximation Register) ADC for CdZnTe (CZT) detectors application. For this SAR ADC, the main-DAC is with charge redistribution architecture to meet with low power dissipation and high speed, and the sub-DAC is a resistive divider to guarantee the linearity. To reduce the mismatches of the capacitances in the charge redistribution, a new architecture using non-lumped capacitor array is proposed, and the corresponding novel switch control algorithm is designed. The novel comparator with offset self-calibrated are proposed to improve the ADCs accuracy. The proposed 12-bit SAR ADC is designed using TSMC 0.35um 2P4M CMOS technology. The simulation results show that, the total conversion time is about 1us, which corresponds to a sampling rate of 1MS/s. The values of the DNL and INL are -0.65~0.52LSB and -0.84~0.65LSB, respectively. The power dissipation is 3mW. The proposed ADC can be utilized in CZT detector systems which are widely used in many applications such as high-energy physics experiments, space exploration and so on.