Yongcai Hu

Nonlinear analysis of microwave FET oscillators using Volterra series

A novel approach for determining the amplitude and frequency of nonlinear FET oscillators is presented. The nonlinear elements of the active device are modeled by the Volterra series method. The frequency and amplitude of oscillation are then calculated by solving two algebraic equations. Experimental results obtained from a constructed oscillator confirm the validity of the theory, the discrepancy between measured and calculated frequency and amplitude values being less than 10%. >

Design and performance of a low-noise, low-power consumption CMOS charge amplifier for capacitive detectors

In this paper, a new design of low noise, low-power consumption charge amplifier is described. Theoretical results show that a total output noise voltage reduction of 0.261 mV has been obtained. This value corresponds to a 46% reduction compared to the noise performance of a conventional charge amplifier. A complete readout system including the proposed charge amplifier has been realized in a 0.8-/spl mu/m semiconductor on insulator (SOI) bipolar complementary metal-oxide-semiconductor (BiCMOS) process. A measured noise performance of 450 electrons at 0 pF with a slope of 44 electrons/pF for a shaping time of 45 ns, a conversion gain of 20 mV/fC and 1-mW power consumption have been obtained.

CMOS pixel sensor for a space radiation monitor with very low cost, power and mass

With the purpose of measuring simultaneously the proton and electron environment using a single sensitive device, we propose a CMOS pixel sensor featuring a 10 mm2 sensitive area, counting capability up to 107/cm2/s and with a minimal error due to pileup of two close particle impacts on the matrix. The proposed architecture includes a 64 × 64 square pixel matrix with 50 μm pitch size, 64 column level 3-bit ADCs to provide an appropriate energy resolution, and an embedded digital logic that directly calculates the particle properties from the hit information provided by the pixels. To validate experimentally the expected performance within the year 2012, a first prototype has been designed and fabricated in a 0.35 μm process without the integrated digital processing part. The device simulation and design architecture are presented.

Methods for predicting dark-current distribution of CMOS image sensor in radiation environment

Nowadays, CMOS image sensors are more and more used in a wide variety of applications, especially in satellite systems, where they are exposed to space radiation environment. In-orbit sensors suffer from radiation induced dark-current degradation that the dark-current mean value and non-uniformity increase, which results in the signal-to-noise-ratio decrease affecting the image quality. Based on the principle of radiation effects on semiconductor devices, this paper analyzes the ionizing and displacement damage effects in CMOS image sensors due to γ-rays and protons radiation, and proposes a method for dark-current distribution modeling in the mixed radiation environment. Simulation results proves that the proposed method is well adapted to predict the dark-current distributions for a device which is exposed to both γ-rays and protons radiation at the same time.

Modeling random telegraph signal noise in CMOS image sensor under low light based on binomial distribution

The random telegraph signal noise in the pixel source follower MOSFET is the principle component of the noise in the CMOS image sensor under low light. In this paper, the physical and statistical model of the random telegraph signal noise in the pixel source follower based on the binomial distribution is set up. The number of electrons captured or released by the oxide traps in the unit time is described as the random variables which obey the binomial distribution. As a result, the output states and the corresponding probabilities of the first and the second samples of the correlated double sampling circuit are acquired. The standard deviation of the output states after the correlated double sampling circuit can be obtained accordingly. In the simulation section, one hundred thousand samples of the source follower MOSFET have been simulated, and the simulation results show that the proposed model has the similar statistical characteristics with the existing models under the effect of the channel length and the density of the oxide trap. Moreover, the noise histogram of the proposed model has been evaluated at different environmental temperatures.

A radiation-hardened low-power pipelined SAR ADC for CZT-based imaging system

A 12-bit 2M Samples/s pipelined SAR ADC for CZT-based imaging system is presented. It pipelines a first stage 6-bit SAR-based Multiplying Digital Analog Converter (MDAC) and a second stage 8-bit SAR ADC. The inter-stage gain of 16 instead of 64 is implemented in the 6-bit SAR-based MDAC for minimizing the power dissipation. The second stage 8-bit SAR ADC uses a split-capacitor architecture for reducing the load capacitance of the residue amplifier and then the power dissipation is minimized. In addition, several radiation-hardened-by-design technologies are adopted at layout design for improving pipelined SAR ADCs radiation tolerance. The prototype chip was fabricated in 0.18 μm mixed-signal 1.8V/3.3V process and occupies a core area of 700μm × 1018 μm. The proposed pipelined SAR ADC achieves 63.7 dB SNDR at 2M Samples/s sampling rate and consumes 12 mW power. The FOM of the proposed ADC is 4.76pJ/conversion-step.

Design of a 10-bit 50MSPS pipeline ADC for CMOS image sensor

This work describes a 10-bit 50MSPS pipeline ADC (Analog-to-Digital Converter) for CMOS (Complementary Metal Oxide Semiconductor) image sensor that is implemented in a TSMC 0.18µm CMOS process. Ten-stage pipeline architecture consists of one-stage sample-and-hold circuit, eight-stage 1.5-bit sub ADC and one-stage 2-bit flash ADC. The digital correction technique is used for calibrating the errors introduced by the comparator. A new digital correction circuit without code conversion circuit is proposed. The presented ADC operates with 3.3V power supply and achieves a power dissipation of 33 mW in typical case. Simulation results show that the values of the DNL (Differential Nonlinearity) and INL (Integral Nonlinearity) are −0.29∼0.30 LSB and −0.29∼0.25 LSB, respectively. The circuit achieves a SNDR (Signal-to-Noise and Distortion Ratio) of 58.28dB and a SFDR (Spurious-Free Dynamic Range) of 64.67dB with a sine wave input of 1.1 V amplitude and 4.93164 MHz frequency. The resulting FOM (Figure of Merit) is 0.984 PJ/conversion step. The proposed ADC in this paper meets the requirements of CMOS image sensor very well.

Design of a novel 12-bit 1MS/s charge redistribution SAR ADC for CZT detectors

This paper presents a novel design of a 12-bit 1MS/s SAR (Successive Approximation Register) ADC for CdZnTe (CZT) detectors application. For this SAR ADC, the main-DAC is with charge redistribution architecture to meet with low power dissipation and high speed, and the sub-DAC is a resistive divider to guarantee the linearity. To reduce the mismatches of the capacitances in the charge redistribution, a new architecture using non-lumped capacitor array is proposed, and the corresponding novel switch control algorithm is designed. The novel comparator with offset self-calibrated are proposed to improve the ADCs accuracy. The proposed 12-bit SAR ADC is designed using TSMC 0.35um 2P4M CMOS technology. The simulation results show that, the total conversion time is about 1us, which corresponds to a sampling rate of 1MS/s. The values of the DNL and INL are -0.65~0.52LSB and -0.84~0.65LSB, respectively. The power dissipation is 3mW. The proposed ADC can be utilized in CZT detector systems which are widely used in many applications such as high-energy physics experiments, space exploration and so on.