Ran Zheng

A 200 mA low-area, low-noise, low-dropout linear regulator for monolithic active pixel sensors

To meet the low-material and low-noise requirements, the power supply of the monolithic active pixel sensors must be improved. This paper presents a built-in low-dropout (LDO) linear regulator to internally supply the analog power. A novel compensation strategy is proposed. Since a series RC network and an adaptively biased buffer are utilized, the location of the poles and zeros vary with that of the output pole. Employing one relative small compensation capacitor, the regulator is stable in the full range of load current. The regulator is designed and simulated in a standard 0.35 μm CMOS process. The chip area is 239 μm × 168 μm. The maximum load current of 200 mA can be obtained. The output spectral noise densities are 320 nV/ V Hz and 110 nV/ V Hz at 100 Hz and 1 kHz, respectively.

A Touch Prediction and Window Sensing Strategy for Low-Power and Low-Cost Capacitive Multitouch Screen Systems

A new multitouch sensing strategy, named the Touch Prediction and Window Sensing (TPWS), is proposed and realized in this paper for projected capacitive touch screens. The detection procedures of TPWS are divided into two stages: a pre-sensing stage for predicting the possible touched regions, and a window sensing stage for obtaining the accurate touched positions. Since the measurements of the untouched sensing cells are reduced significantly, the TPWS strategy needs lower efforts on signal readout and data processing than the traditional strategies. A prototype system was designed and realized, which consists of three identical 48-channel readout chips, a 15-in capacitive touch screen, and a commercial host processor. The readout chip is specially designed for the TPWS strategy using 0.13 μm 1.8 V/5 V CMOS process. The measurement results show that, the total power consumption of the system is only about 65 mW with a power supply of 5 V, and the reporting rate of the system achieves 500 Hz for no touches and 83 Hz for ten touches. The area of the readout chip is only 0.087 mm2 per sensing channel. The proposed TPWS strategy can be used to realize low-power and low-cost multitouch screen system, and it is especially efficient for large-sized screen.

Design of a Multi-Channel Low-Noise Readout ASIC for CdZnTe-Based X-Ray and

In this paper, we report on the recent development of a 32-channel low-noise front-end readout ASIC for cadmium zinc telluride (CdZnTe) X-ray and γ-ray detectors. Each readout channel includes a charge sensitive amplifier, a CR-RC shaping amplifier and an analog output buffer. The readout ASIC is implemented using TSMC 0.35 - μm mixed-signal CMOS technology, the die size of the prototype chip is 2.2 mm ×4.8 mm. At room temperature, the equivalent noise level of a typical channel reaches 133 e- (rms) with the input parasitic capacitance of 0 pF for the average power consumption of 2.8 mW per channel. The linearity error is less than ±2% and the input energy dynamic range of the readout ASIC is from 10 keV to 1 MeV. The crosstalk between the channels is less than 0.4%. By connecting the readout ASIC to a CdZnTe detector, we obtained a γ-ray spectrum, the energy resolution is 1.8% at the 662-keV line of 137Cs source.

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In this paper, a DC-coupling readout circuit is presented in order to readout the signal from CdZnTe detectors. A differential stage is added in CSA to compensate the leakage current introduced by the CdZnTe crystal. A compact shaper is designed to achieve low area with wide range of adjustable peaking time from 3 μ s to 10 μ s. The area of proposed circuit is about 130 μ m × 1100 μ m. The experimental results show that the ENC is 70 e− + 14 e−/pF and the gain is about 152 mV/fC at the peaking time of 4 μ s.

-Ray Spectrum Analyzer

Temporal noise sources in 4-T pinned photodiode (PPD) active-pixel-sensor (APS) are analyzed basing on a typical APS pixel structure working during reset, integration and readout operation. Complete reset operation and incomplete reset operation result in different reset noise power. Incomplete reset can realize lower noise power but cause image lag. To cover the problem a “pre-reset” technique for 4-T PPD APS is proposed. Analysis also indicates that, in most situations, the integration noise dominates the reset noise, even under complete reset operation. So, another method using higher gate-controlling voltage is proposed to implement complete reset to alleviate image lag and the dynamic range is improved as well. Taking reset noise, integration noise and readout noise into consideration, the pixels output SNR (signal to noise ratio) is analyzed and optimized at C<inf>FD</inf>/C<inf>PH</inf> = kT/(C<inf>PH</inf>V²<inf>n, in</inf>), in which, C<inf>PH</inf> and C<inf>FD</inf> are the equivalent capacitors of the photodiode and floating-node (FD) in the pixel, V²<inf>n, in</inf> is the input-referred noise of the in-pixel follower.

A DC-coupling area-efficiency readout circuit for CdZnTe detectors

CMOS Active pixel sensors (CMOS APS) are attractive for use in the innermost layers of charged particle trackers, due to their good tradeoffs among the key performances. However, CMOS APS can be greatly influenced by random telegraph signal (RTS) noise, which can cause particle tracking or energy calculation failures. In-depth research of pixels RTS behavior stimulates the interest of the methods for RTS noise detection, reconstruction and parameters extraction. In this paper, a real-time auto-detection method is proposed, using real-time Gaussian noise standard deviation as the detection threshold. Experimental results show that, compared with current methods using signal standard deviation as the thresholds, the proposed method is more sensitive in multi-level RTS detection and more effective in the case of RTS noise degradation.

Temporal noise analysis and optimizing techniques for 4-T pinned photodiode active pixel sensor

CMOS pixel sensors (CPS) are attractive for use in the innermost particle detectors for charged particle tracking due to their good trade-off between spatial resolution, material budget, radiation hardness, and readout speed. With the requirements of high readout speed and high radiation hardness to total ionizing dose (TID) for particle tracking, fast readout CPS are composed by integrating a data compression block and two SRAM IP cores. However, the radiation hardness of the SRAM IP cores is not as high as that of the other parts in CPS, and thus the radiation hardness of the whole CPS chip is lowered. Especially, when CPS are migrated into 0.18-μm processes, the single event upset (SEU) effects should be also considered besides TID and single event latchup (SEL) effects. This paper presents a radiation-hardened SRAM with enhanced radiation hardness to SEU. An error detection and correction (EDAC) algorithm and a bit-interleaving storage strategy are adopted in the design. The prototype design has been fabricated in a 0.18-μm process. The area of the new SRAM is increased 1.6 times as compared with a non-radiation-hardened SRAM due to the integration of EDAC algorithm and the adoption of radiation hardened layout. The access time is increased from 5 ns to 8 ns due to the integration of EDAC algorithm. The test results indicate that the design satisfy requirements of CPS for charged particle tracking.

A Real-time Auto-detection Method for Random Telegraph Signal (RTS) Noise Detection in CMOS Active pixel sensors

Analysis on the noise caused by dark-current (black level noise) and offset voltages in CMOS image sensor is implemented and a 10 bit pipelined ADC with the function of eliminating the noise is proposed in this paper. Through Connecting a calibration voltage to one input of the SH circuit in Pipeline ADC, the black level noise and offset noise is eliminated. According to the working mode, the input dynamic range of the proposed pipelined ADC can be adjusted through a digital module. As a result, dynamic range is improved by 6.02 dB when the ADC is working on signal-sampling mode. Simulation results show the pipelined ADC has a DNL(Differential Nonlinearity) of +0.41/ − 0.59 LSB, INL(Integral Nonlinearity) of +1.64/ − 1.57 LSB. The SNR is 59.61 dB and ENOB(Effective Number of Bits) is 9.39 bits.

Development of a radiation-hardened SRAM with EDAC algorithm for fast readout CMOS pixel sensors for charged particle tracking

Nowadays, CMOS image sensors are more and more used in a wide variety of applications, especially in satellite systems, where they are exposed to space radiation environment. In-orbit sensors suffer from radiation induced dark-current degradation that the dark-current mean value and non-uniformity increase, which results in the signal-to-noise-ratio decrease affecting the image quality. Based on the principle of radiation effects on semiconductor devices, this paper analyzes the ionizing and displacement damage effects in CMOS image sensors due to γ-rays and protons radiation, and proposes a method for dark-current distribution modeling in the mixed radiation environment. Simulation results proves that the proposed method is well adapted to predict the dark-current distributions for a device which is exposed to both γ-rays and protons radiation at the same time.

Dynamic-range adjustable pipelined ADC in CMOS image sensor with black-level and offset noise calibration

In order to read out the signal of CdZnTe detectors, this paper presents a high-gain, third-order analogue signal processing application specific integrated circuit (ASIC). The charge generated in detectors can be amplified and shaped by this circuit. Dual-stage charge sensitive amplifier and baseline holder are utilized to compensate the leakage current from DC-coupled detectors. A novel shaper is proposed to improve the output amplitude and achieve high gain. A high-order shaper in our previous work is also presented for comparison. The proposed ASIC has been designed and verified in a standard commercial 2P4M 0.35μm CMOS process. The die area of one channel is 975 μm × 142 μm. The gain is 185 mV/fC at the peaking time of 1 μs. The peaking time can be adjusted from 1 μs to 3 μs. The maximum leakage current of 5 nA can be compensated.