Tobias Gemmeke

METHOD AND SYSTEM FOR VERIFYING THE EQUIVALENCE OF DIGITAL CIRCUITS

Formally deriving a minimal clock-gating scheme

INSTRUCTION SET ARCHITECTURE WITH DECOMPOSING OPERANDS

SEMICONDUCTOR CHIP WITH A PLURALITY OF SCANNABLE STORAGE ELEMENTS AND A METHOD FOR SCANNING STORAGE ELEMENTS ON A SEMICONDUCTOR CHIP

Permute Unit and Method to Operate a Permute Unit

Circuit Arrangement and Method to Reduce Leakage Power and to Increase the Performance of a Circuit

Reducing register file leakage current within a processor

Method to Reduce Leakage Within a Sequential Network and Latch Circuit

System and Method for Scanning Sequential Logic Elements

Method and Apparatus for Performing Equivalence Checking on Circuit Designs Having Differing Clocking and Latching Schemes