Tod D. Wolf | Researchain

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international conference on vlsi design | 2004

A 800 MHz system-on-chip for wireless infrastructure applications

Sanjive Agarwala; Paul Wiley; Arjun Rajagopal; Anthony M. Hill; Raguram Damodaran; Lewis Nardini; Timothy D. Anderson; Steven Mullinnix; Jose Luis Flores; Heping Yue; Abhijeet Ashok Chachad; John Apostol; Kyle Castille; Usha Narasimha; Tod D. Wolf; N. S. Nagaraj; Manjeri Krishnan; Luong Nguyen; Todd Kroeger; Michael Gill; Peter Groves; Bill Webster; Joel J. Graber; Christine Karlovich

The 800MHz System-on-Chip implements the C64x VLIW DSP VelociTI.2/spl trade/ Architecture and delivers 6400 MIPS, 3200 16-bit MMACs, 6400 8-bit MMACs at 0.17 mW/MMAC (8 bit). The chip is implemented in state of the art 90 nm CMOS technology with 7-layer copper metalization. The core dissipates 1080 mW at 800 MHz, 1.2V. The system-on-chip is targeted for high performance wireless infrastructure application. It has an 8-way VLIW DSP core, a 2-level memory system, and an I/O bandwidth of 3.2GB/s.

custom integrated circuits conference | 2002

600 MHz DSP for baseband processing in 3G base stations

Tod D. Wolf; Dale E. Hocevar; Alan Gatherer; Patrick Geremia; Armelle Laine

A 1.2 V 600 MHz 4800 MIPS DSP is a solution for baseband processing in 3G base stations. It is based upon a partitioning of the workload between a DSP core and two flexible forward error correction coprocessors. This allows the DSP to handle a larger number of channels and/or to incorporate advanced algorithms.

Archive | 1999