Tom Bonifield

Development of a stacked WCSP package platform using TSV (Through Silicon Via) technology

To enable the miniaturization, electrical performance and heterogeneous functionality needs for emerging Analog applications, a stacked Wafer-level Chip Scale Package (WCSP) package platform has been developed using Through-Silicon Via (TSV) technology. This allows stacking of ICs, MEMS, passives and other components in the vertical direction onto active or passive TSV wafers, to create innovative System-in-Package (SiP) product solutions. Since Analog devices are small in size and cost is a key care about, a careful selection of the integration flow is required to achieve a low cost packaging solution. In this work, an integration flow for the stacked WCSP package is presented, along with development details for the Chip-on-Wafer (CoW) bonding and wafer overmolding unit processes. The test vehicle was 3mm × 3mm in size and used 25u diameter Cu TSVs in a 200mm diameter wafer. Interconnect reliability evaluations were done with different micro-bump Under Bump Metallurgy (UBM) and TSV tip surface finish metallization combinations. Wafer ovemolding development included warpage, saw and adhesion evaluations with multiple mold materials. A back-end assembly flow was established with a mass reflow bonding process and an overmold material with low CTE and intermediate Tg and modulus. Samples were prepared with mold-on-die and exposed die package structures. Excellent time-zero yields were obtained, with an average TSV micro-bump interconnect resistance of 25 mohms. Results and failures modes from preliminary reliability testing are included.

Benchmarks for interconnect parasitic resistance and capacitance

Interconnect parasitics are dominating circuit performance, signal integrity and reliability in IC design. Copper/low-k process effects are becoming increasingly important to accurately model interconnect parasitics. Even if the interconnect process profile is accurately represented, approximations in parasitic extraction could cause large errors. Typically, researchers and designers have been using pre-defined set of structures to validate the accuracy of interconnect models and parasitic extraction tools. Unlike industry benchmarks on circuits such as MCNC benchmarks, no benchmarks exist for interconnect parasitics. This paper discusses the issues in accurate interconnect modeling for 130 nm and below copper/ultra low-k technologies. A set of benchmark structures that could be used to validate accuracy and compare parasitic extraction tools is proposed. Silicon results from 130 nm technology are presented to illustrate the usefulness of these benchmarks. Results of application of these benchmarks to compare parasitic extraction tools are presented to demonstrate systematic validation of resistance and capacitance extraction.

BEOL variability and impact on RC extraction

Historically, back end of line (BEOL) or interconnect resistance and capacitance have been viewed as parasitic components. They have now become key parameters with significant impact on circuit performance and signal integrity. This paper examines the types of BEOL variations and their impact on RC extraction. The importance of modeling systematic effects in RC extraction is discussed. The need for minimizing the computational error in RC extraction before incorporating random process variations is emphasized.

Effect of intermetallic formation on electromigration reliability of TSV-microbump joints in 3D interconnect

In this study, electromigration (EM) reliability of TSV-microbump (μ-bump) joints was investigated. Sn-based μ-bumps with three different schemes of metallization were tested under current stressing at elevated temperatures. EM-stressed μ-bumps, together with thermal anneal-only μ-bumps and as-received controls, were cross-sectioned and characterized using scanning electron microscope (SEM), energy dispersed x-ray (EDX) and focused ion beam (FIB). Intermetallic compound (IMC) growth kinetics under EM for the three types of metallization were obtained, and compared with those subjected to thermal annealing only. Results showed good EM performance of the TSV μ-bump joints, indicating that IMC formation plays an important role in improving the EM reliability of μ-bump joints. However, non-EM related voids were observed in the μ-bumps, and the voiding mechanisms were discussed.

Hillocks on half-micron aluminum lines

A new regime of hillock growth has been observed in patterned Al 98.5 W.% Si 1.0 Wt.% -Cuo 0.5 wt.% films. The “surface” hillock and “side” hillock, which have been seen previously, form on patterned metal lines having linewidths greater than the larger Al alloy grain sizes (∼3 μm). None is seen on the fabricated lines having linewidths between 0.9 and 2 μm where long-range grain boundary diffusion cannot occur because of its bamboo structure. However, a new type of hillock, the “line hillock”, occurs in structures having linewidths of 0.6 μm. The presence of this last type of hillock is inconsistent with the current understanding of hillock formation and may present severe restrictions on the down-sizing of ultra–large–scale integrated devices.

Interconnect modeling for copper/low-k technologies

Interconnect parasitics are significant and complex components of circuit performance, signal integrity and reliability in IC design. Copper/low-k process effects are becoming increasingly important to accurately model interconnect parasitics. In this tutorial, four key aspects of copper/low-k interconnect process are discussed: Non-linear resistance, Selective Process Bias (SPB), dummy (fill) metal and process variations. Even if the interconnect process profile is accurately represented, approximations in parasitic extraction could cause large errors. Techniques used in parasitic extraction to model the copper/low-k effects are discussed in detail. Techniques to measure resistance and capacitance in silicon and correlating them to parasitic extraction tools are presented to demonstrate systematic validation interconnect parasitics.

The properties of thermal hillocks as a function of linewidth and process parameter in Al-on-chemical-vapor-deposited W films

patterned and unpatterned Al98.5wt. %Si1.0wt. %Cu0.5wt. % films deposited on chemical-vapordeposited W-coated substrates. The effects of linewidth, substrate temperature during film deposition, and sintering time and temperature on hillock size were investigated. Three types of hillocks are found: the “surface hillocks”, the “side hillock”, and the “line hillock”. These are further classified by their shapes. The surface hillock and side hillock, which have been seen previously, form on patterned metal lines having linewidths greater than the larger Al alloy grain sizes (,3 mm). None is seen on linewidths between 0.9 and 2 mm where long-range grain boundary diffusion cannot occur. A new type of hillock, the line hillock, is seen to occur on metal structures having linewidths of 0.6 mm. The line hillock is inconsistent with the current understanding of hillock formation and may present severe restrictions on the downsizing of ultra-large-scale integrated devices.

A systematic approach to interconnect modeling and process monitoring

This paper describes a systematic approach to the use of electrical measurements for interconnect modeling and process monitoring. A fast and area efficient technique to measure interconnect capacitance in a scribe line is discussed. The benefits of this technique in monitoring interconnect process, and in fanning out technology to multiple fabs, in monitoring wafer-to-wafer/lot-to-lot variations and in accurate modeling of capacitance are illustrated using the results from 130 nm copper technology.