Rajiv Dunne

Development of a stacked WCSP package platform using TSV (Through Silicon Via) technology

To enable the miniaturization, electrical performance and heterogeneous functionality needs for emerging Analog applications, a stacked Wafer-level Chip Scale Package (WCSP) package platform has been developed using Through-Silicon Via (TSV) technology. This allows stacking of ICs, MEMS, passives and other components in the vertical direction onto active or passive TSV wafers, to create innovative System-in-Package (SiP) product solutions. Since Analog devices are small in size and cost is a key care about, a careful selection of the integration flow is required to achieve a low cost packaging solution. In this work, an integration flow for the stacked WCSP package is presented, along with development details for the Chip-on-Wafer (CoW) bonding and wafer overmolding unit processes. The test vehicle was 3mm × 3mm in size and used 25u diameter Cu TSVs in a 200mm diameter wafer. Interconnect reliability evaluations were done with different micro-bump Under Bump Metallurgy (UBM) and TSV tip surface finish metallization combinations. Wafer ovemolding development included warpage, saw and adhesion evaluations with multiple mold materials. A back-end assembly flow was established with a mass reflow bonding process and an overmold material with low CTE and intermediate Tg and modulus. Samples were prepared with mold-on-die and exposed die package structures. Excellent time-zero yields were obtained, with an average TSV micro-bump interconnect resistance of 25 mohms. Results and failures modes from preliminary reliability testing are included.

Low temperature, low profile, ultra-fine pitch copper-to-copper chip-last embedded-active interconnection technology

In a continuous drive to achieve low form-factor packages, chip-to-package interconnections have evolved from the conventional solders to a more hybrid technology consisting of copper and solder. However, scaling down the bump pitch to increase the interconnect density poses serious reliability and yield issues. In the previous, a low-profile interconnect architecture, ~20µm total height, was demonstrated comprising of copper-to-copper interconnection and novel adhesive materials. This paper focuses on: (1) design and fabrication of test vehicles to assess the robustness of the interconnect architecture, (2) assembly process development for copper-to-copper interconnections, and (3) reliability and failure analysis of the interconnection. Excellent reliability results are demonstrated under thermal cycling test (TCT) using non-conductive films (NCF) as adhesive. This interconnect scheme is also shown to perform well with different die sizes, die thicknesses and with embedded dies thus offering a great potential for integration with flip chip packages as well as with chip-last embedded active chips in organic substrates. A simple and reliable low-cost and low-temperature direct Cu-Cu bonding is thus demonstrated for the first time.

Effect of intermetallic formation on electromigration reliability of TSV-microbump joints in 3D interconnect

In this study, electromigration (EM) reliability of TSV-microbump (μ-bump) joints was investigated. Sn-based μ-bumps with three different schemes of metallization were tested under current stressing at elevated temperatures. EM-stressed μ-bumps, together with thermal anneal-only μ-bumps and as-received controls, were cross-sectioned and characterized using scanning electron microscope (SEM), energy dispersed x-ray (EDX) and focused ion beam (FIB). Intermetallic compound (IMC) growth kinetics under EM for the three types of metallization were obtained, and compared with those subjected to thermal annealing only. Results showed good EM performance of the TSV μ-bump joints, indicating that IMC formation plays an important role in improving the EM reliability of μ-bump joints. However, non-EM related voids were observed in the μ-bumps, and the voiding mechanisms were discussed.

Measurement of impact toughness of eutectic SnPb and SnAgCu solder joints in ball grid array by mini-impact tester

The most frequent cause of failure for wireless, handheld, and portable consumer electronic products is an accidental drop to the ground. The impact may cause interfacial fracture of ball-grid-array solder joints. Existing metrology, such as ball shear and ball pull tests, cannot characterize the impact-induced high speed fracture failure. In this study, a mini-impact tester was utilized to measure the impact toughness and to characterize the impact reliability of both eutectic SnPb and SnAgCu solder joints. The annealing effect at 150 °C on the impact toughness was investigated, and the fractured surfaces were examined. The impact toughness of SnAgCu solder joints with the plating of electroless Ni/immersion Au (ENIG) became worse after annealing, decreasing from 10 or 11 mJ to 7 mJ. On the other hand, an improvement of the impact toughness of eutectic SnPb solder joints with ENIG was recorded after annealing, increasing from 6 or 10 to 15 mJ. Annealing has softened the bulk SnPb solder so that more plastic deformation can occur to absorb the impact energy.

A coaxial probe system for measuring Z-direction electrical resistivity of conductive polymers

A novel coaxial Kelvin probe technique has been developed to measure the z-axis electrical resistivity of conductive polymer adhesives. The approach uses a very simple test structure, comprising of a sandwich of the conductive adhesive material between two Copper conductors. The coaxial probe includes an outer region through which the current is forced, and an inner probe which senses the surface voltage drop, and is hooked to a nano-voltmeter to enable micro-ohms resistance measurements with high sensitivity. This is followed by detailed finite element modeling of the sample and probe set-up configuration to extract an accurate value for the effective z-axis resistivity of the conductive adhesive, as well as its bulk and interfacial z-resistivity values. This technique has been demonstrated on two candidate conductive materials as well as solder (as a reference). It has the potential to enable rapid optimization and development of conductive polymer adhesive systems for different interfaces and for various applications.