Tomasz Borejko

A resistorless current reference source for 65 nm CMOS technology with low sensitivity to process, supply voltage and temperature variations

A reistorless current reference source, e.g. for fast communication interfaces, has been described. Addition of currents with opposite temperature coefficient (PTC and NTC) and body effect have been used to temperature compensation. Cascode structures have been used to improve the power supply rejection ratio. The reference current source has been designed in a GLOBALFOUNDRIES 65 nm technology. The presented circuit achieves 55 ppm/°C temperature coefficient over range of −40 °C to 125 °C. Reference current susceptibility to process parameters variation is ±3 %. The power supply rejection ratio without any filtering capacitor at 100 Hz and 10 MHz is lower than −127 dB and −103 dB, respectively.

CAD tool for PLL Design

In this paper PLL Design tool, created in Matlab from MathWorks, has been presented. The tool allows to analyze loop stability and phase noise of PLL, based on phase-locked loop linear model. Fast evaluation of loop filter components values for popular passive and active filters is possible. The created tool allows to analyze PLL parameters, like loop filter components values, VCO gain and charge pump current variations impact on loop stability and phase-noise. Algorithm for phase-noise calculation, based on transient PLL simulation, has also been implemented. Thanks to these features the created tool is a valuable aid for PLL designer on all design steps.

A Resistorless Voltage Reference Source for 90 nm CMOS Technology with Low Sensitivity to Process and Temperature Variations

A new compact low power voltage reference source for wireless and embedded applications is described. The reference voltage source has been designed in a mixed-signal UMC 90 nm CMOS process using subthreshold characteristics for generating a constant voltage of 423 mV at supply voltages from 1.1 V to 3.3 V with total current consumption 270 nA. The proposed circuit occupies 0.001 mm2 chip area and achieves less than 110 ppm/degC for all process corners and temperature variation from -40degC to 125 degC. The power supply rejection ratio without any filtering capacitor at 100 Hz and 10 MHz is lower than -50 dB and -30 dB, respectively. The equivalent output voltage noise in the bandwidth from 1 Hz to 10 MHz reaches 218 muVRMS.

LC-VCO design automation tool for nanometer CMOS technology

In this paper a low-voltage LC voltage-controlled oscillator (VCO) design automation tool has been presented. The tool is based on design methodology, which takes under consideration trade-offs between power consumption, phase noise and tuning range. NMOS only architecture is considered because of its capability to work with low supply voltages. One of the goals, while creating the tool, was to make it technology independent. This was achieved by creating SKILL scripts that allows fast configuration of design library for specified technology. Trade-offs between power consumption, phase noise and tuning range are analyzed and based on them design flow has been proposed. Finally two design examples in 90 and 130 nm CMOS technology have been presented.

BioSoC: Highly integrated System-on-Chip for health monitoring

The BioSoC is a highly integrated SoC that consists of analog front-ends, analog to digital converters and a 32-bit microcontroller - Adelite. The designed IC allows for dynamic acquisition and processing of the most important human physiological parameters. The provided analog interfaces to external electrodes and sensors allow measurement of electrocardiograms (ECG), electromyograms (EMG), skin temperature and resistance, and respiration rate (RR). After analog processing signals are sampled and digitized in analog-to-digital converters they can be further processed in a 32-bit microcontroller Adelite. The clock frequency of the microprocessor core is configurable from 32 kHz up to 16 MHz. The microcontroller is equipped with many digital interfaces and peripherals, such as 2×UART and 2×SPI with DMA channels, 16 GPIOs and 5 timers along with RTC. The BioSoC makes it possible to build highly integrated devices with rich functionalities in the area of telemedicine that respond to the growing demand for portable health monitoring. The BioSoC was designed and fabricated in UMC CMOS 130 nm technology process and occupies the area of 25mm2.

A comparison of low voltage LNA architectures designed for multistandard GNSS in two 90 nm CMOS technologies

In this paper a comparison of two low noise amplifiers (LNAs) designed in two 90 nm CMOS technologies (so called A and B) has been made. For each technology two LNA topologies were simulated: inductively degenerated cascode (LC), which achieves high gain and low noise figure (NF), and folded cascode (FC), which can work with low supply voltage. These amplifiers were designed for a GPS/Galileo receiver. Chosen circuits demonstrate gains of 16.42 dB, 17.27 dB, 14.51 dB and 14.41 dB, consuming currents 2.492 mA, 3.093 mA, 2.834 mA and 4.609 mA with NFs equal to 1.881 dB, 1.914 dB, 2.345 dB and 2.427 dB for LC and FC architecture in A and B technologies respectively. For all amplifiers the supply voltage is 0.6 V.

Low voltage LNA implementations in 90 nm CMOS technology for multistandard GNSS

In this paper, two topologies of CMOS low noise amplifiers (LNAs) have been simulated. The inductively degenerated cascode (LC), which achieves high gain and low noise figure (NF), and folded cascode (FC), which can work with ultra low supply voltage, were considered. LNAs were optimized for a GPS/Galileo receiver using UMC 90 nm CMOS technology. Chosen circuits demonstrate a gain of 16.42 dB and 17.27 dB, consuming current 2.492 mA and 3.093 mA, showing NF 1.881 dB and 1.914 dB, third order input interception point (IIP3) −14.99 dBm and −13.3 dBm, input referred 1-dB compression point (Pin-1) −29 dBm and −29.47 dBm for inductively degenerated cascode and folded cascode respectively. Both input return loss (S11) and output return loss (S22) are below −40 dB. For these circuits supply voltage is 0.6 V and die area equals 0.33 mm2.

Built-In Current Monitor for IDDQ Testing in CMOS 90 nm Technology

In this paper, a built-in current (BIC) monitor for testing low-voltage digital CMOS circuits is presented. The monitor is designated for typical IDDQ testing as well as for characterization of supply current values for different test vectors. Voltage drop across the monitor during measurement and the switching phase are minimized. A wide range of currents is supported. Abilities and limitations of the BIC monitor were verified through simulations. Results of post layout simulations are presented as well. The design was implemented in UMC CMOS 90 nm technology.

The integrated transmitter and receiver modules for pulse oximeter system

This paper deals with the design and implementation of transmitter and receiver modules for pulse oximeter system. First, the fundamentals of noninvasive method for monitoring the oxygen saturation are briefly described. Next, two proposed modules and their monolithic implementations are presented and discussed. These sections describe the integrated transmitter and receiver circuits intended to work with transmitting and receiving diodes respectively. Several important simulation results are shown, including analysis proving proper cooperation between designed modules. Finally, brief summary has been made at the end of the article, describing future development of proposed solutions.

Dedicated chip for pulse oximetry measurements

This paper presents the design and implementation of the integrated circuit aimed at pulse oximetry measurements and intended to be a part of the biomedical SoC. The basics of the noninvasive method for oxygen saturation monitoring are briefly described and then the overview of the designed chip is presented and discussed. Next, several important simulation results are shown, proving proper operation of the designed structure.